forked from M-Labs/artiq
sayma: use GTP_CLK1 only for all variants (#1080)
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e2a49ce368
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@ -169,12 +169,9 @@ pub mod hmc7043 {
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(true, SYSREF_DIV, 0x08), // 3: DAC1_SYSREF
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(false, 0, 0x08), // 4: ADC2_CLK
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(false, 0, 0x08), // 5: ADC2_SYSREF
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(true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2
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(false, 0, 0x08), // 6: GTP_CLK2
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(true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS
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#[cfg(hmc7043_enable_clk1)]
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(true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1
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#[cfg(not(hmc7043_enable_clk1))]
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(false, 0, 0x08), // 8: GTP_CLK1
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(false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK
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(false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK
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(true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser
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@ -27,7 +27,7 @@ class UltrascaleCRG(Module, AutoCSR):
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self.clock_domains.cd_jesd = ClockDomain()
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refclk2 = Signal()
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refclk_pads = platform.request("dac_refclk", 1)
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refclk_pads = platform.request("dac_refclk", 0)
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platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
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self.specials += [
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Instance("IBUFDS_GTE3", i_CEB=self.ibuf_disable.storage, p_REFCLK_HROW_CK_SEL=0b00,
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@ -269,17 +269,19 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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attr={("DONT_TOUCH", "true")})
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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self.csr_devices.append("ad9154_crg")
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self.comb += [
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platform.request("sfp_tx_disable", i).eq(0)
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for i in range(2)
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("dac_refclk", 0),
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clock_pads=self.ad9154_crg.refclk,
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data_pads=[platform.request("sfp", i) for i in range(2)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.config["HMC7043_ENABLE_CLK1"] = None
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drtio_csr_group = []
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drtio_memory_group = []
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@ -332,14 +334,12 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_crg")
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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@ -577,12 +577,11 @@ class Satellite(BaseSoC, RTMCommon):
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("dac_refclk", 0),
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clock_pads=self.ad9154_crg.refclk,
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.config["HMC7043_ENABLE_CLK1"] = None
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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