From 493d2a653f01abcee5db8c9d9897655f29c11a0e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 29 Mar 2018 10:55:41 +0800 Subject: [PATCH] siphaser: add false path between sys_clk and mmcm_freerun_output --- artiq/gateware/targets/kasli.py | 5 +++-- artiq/gateware/targets/sayma_amc.py | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index c35dabce7..b9f8320bb 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -791,8 +791,9 @@ class _SatelliteBase(BaseSoC): self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), - si5324_clkout_fabric=platform.request("si5324_clkout_fabric") - ) + si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 116ce75c6..a27c59fac 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -439,10 +439,11 @@ class Satellite(BaseSoC): self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), - si5324_clkout_fabric=platform.request("si5324_clkout_fabric") - ) + si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", mmcm_ps=self.siphaser.mmcm_ps_output) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n")