forked from M-Labs/artiq
siphaser: add false path between sys_clk and mmcm_freerun_output
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4229c045f4
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493d2a653f
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@ -791,8 +791,9 @@ class _SatelliteBase(BaseSoC):
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
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)
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si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -439,10 +439,11 @@ class Satellite(BaseSoC):
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkout_fabric=platform.request("si5324_clkout_fabric")
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)
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si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
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platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
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mmcm_ps=self.siphaser.mmcm_ps_output)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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