From 470bce621435b155ea8eb705839416d70e912b5e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 20 Jun 2017 00:48:50 +0800 Subject: [PATCH] coredevice: add AD9154 SPI access driver --- artiq/coredevice/ad9154_spi.py | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 artiq/coredevice/ad9154_spi.py diff --git a/artiq/coredevice/ad9154_spi.py b/artiq/coredevice/ad9154_spi.py new file mode 100644 index 000000000..0ebb77034 --- /dev/null +++ b/artiq/coredevice/ad9154_spi.py @@ -0,0 +1,24 @@ +from artiq.language.core import kernel + + +class AD9154: + """Kernel interface to AD9154 registers, using non-realtime SPI.""" + + def __init__(self, dmgr, spi_device, chip_select): + self.core = dmgr.get("core") + self.bus = dmgr.get(spi_device) + self.chip_select = chip_select + + @kernel + def setup_bus(self, write_div=16, read_div=16): + self.bus.set_config_mu(0, write_div, read_div) + self.bus.set_xfer(self.chip_select, 24, 0) + + @kernel + def write(self, addr, data): + self.bus.write((addr << 16) | (data<< 8)) + + @kernel + def read(self, addr): + self.write((1 << 15) | addr, 0) + return self.bus.read()