forked from M-Labs/artiq
moninj: fix underflows by order of operation
fix channel toggle
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parent
c9fb7b410f
commit
46f2842d38
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@ -560,7 +560,7 @@ class _DeviceManager:
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if len(cfg) > 0:
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self.{cpld}.cfg_reg = cfg[0]
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else:
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delay(10*ms)
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delay(15*ms)
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self.{cpld}.init()
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self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
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cfg = self.core_cache.get("_{cpld}_cfg")
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@ -584,8 +584,8 @@ class _DeviceManager:
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@kernel
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def run(self):
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self.core.reset()
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delay(5*ms)
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{cpld_init}
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delay(5*ms)
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self.{dds_channel}.init()
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self.{dds_channel}.set({freq})
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{cfg_sw}
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@ -598,7 +598,7 @@ class _DeviceManager:
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"SetDDS",
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"Set DDS {} {}MHz".format(dds_channel, freq/1e6)))
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def dds_channel_toggle(self, dds_model, sw=True):
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def dds_channel_toggle(self, dds_channel, dds_model, sw=True):
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# urukul only
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toggle_exp = textwrap.dedent("""
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from artiq.experiment import *
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@ -612,16 +612,16 @@ class _DeviceManager:
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@kernel
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def run(self):
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self.core.break_realtime()
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delay(5*ms)
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self.core.reset()
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cfg = self.core_cache.get("_{cpld}_cfg")
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if len(cfg) > 0:
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self.{cpld}.cfg_reg = cfg[0]
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else:
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delay(10*ms)
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delay(15*ms)
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self.{cpld}.init()
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self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
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cfg = self.core_cache.get("_{cpld}_cfg")
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delay(5*ms)
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self.{ch}.init()
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self.{ch}.cfg_sw({sw})
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cfg[0] = self.{cpld}.cfg_reg
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