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kc705_drtio_satellite: add MiSoC system, hook up auxiliary controller

This commit is contained in:
Sebastien Bourdeauducq 2016-12-06 14:56:42 +08:00
parent f4b7d39a69
commit 4669d3f02f
1 changed files with 38 additions and 29 deletions

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@ -2,18 +2,21 @@ import argparse
from migen import * from migen import *
from migen.build.generic_platform import * from migen.build.generic_platform import *
from migen.build.platforms import kc705
from misoc.cores.i2c import * from misoc.cores.i2c import *
from misoc.cores.sequencer import * from misoc.cores.sequencer import *
from misoc.integration.builder import *
from misoc.integration.soc_core import mem_decoder
from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import gtx_7series from artiq.gateware.drtio.transceiver import gtx_7series
from artiq.gateware.drtio import DRTIOSatellite from artiq.gateware.drtio import DRTIOSatellite
from artiq import __version__ as artiq_version
# TODO: parameters for sawg_3g # TODO: parameters for sawg_3g
# TODO: move I2C programming to softcore CPU
def get_i2c_program(sys_clk_freq): def get_i2c_program(sys_clk_freq):
# NOTE: the logical parameters DO NOT MAP to physical values written # NOTE: the logical parameters DO NOT MAP to physical values written
# into registers. They have to be mapped; see the datasheet. # into registers. They have to be mapped; see the datasheet.
@ -121,9 +124,21 @@ fmc_clock_io = [
] ]
class Satellite(Module): class Satellite(BaseSoC):
def __init__(self, cfg, medium, toolchain): mem_map = {
self.platform = platform = kc705.Platform(toolchain=toolchain) "drtio_aux": 0x60000000,
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, cfg, medium, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
**kwargs)
platform = self.platform
rtio_channels = [] rtio_channels = []
for i in range(8): for i in range(8):
@ -135,16 +150,9 @@ class Satellite(Module):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
sys_clock_pads = platform.request("clk156")
self.clock_domains.cd_sys = ClockDomain(reset_less=True)
self.specials += Instance("IBUFGDS",
i_I=sys_clock_pads.p, i_IB=sys_clock_pads.n,
o_O=self.cd_sys.clk)
sys_clk_freq = 156000000
i2c_master = I2CMaster(platform.request("i2c")) i2c_master = I2CMaster(platform.request("i2c"))
sequencer = ResetInserter()(Sequencer(get_i2c_program(sys_clk_freq))) sequencer = ResetInserter()(Sequencer(get_i2c_program(self.clk_freq)))
si5324_reset_clock = Si5324ResetClock(platform, sys_clk_freq) si5324_reset_clock = Si5324ResetClock(platform, self.clk_freq)
self.submodules += i2c_master, sequencer, si5324_reset_clock self.submodules += i2c_master, sequencer, si5324_reset_clock
self.comb += [ self.comb += [
sequencer.bus.connect(i2c_master.bus), sequencer.bus.connect(i2c_master.bus),
@ -168,7 +176,7 @@ class Satellite(Module):
clock_pads=platform.request("sgmii_clock"), clock_pads=platform.request("sgmii_clock"),
tx_pads=tx_pads, tx_pads=tx_pads,
rx_pads=rx_pads, rx_pads=rx_pads,
sys_clk_freq=sys_clk_freq, sys_clk_freq=self.clk_freq,
clock_div2=True) clock_div2=True)
elif cfg == "sawg_3g": elif cfg == "sawg_3g":
# 3Gb link, 150MHz RTIO clock # 3Gb link, 150MHz RTIO clock
@ -178,33 +186,32 @@ class Satellite(Module):
clock_pads=platform.request("ad9154_refclk"), clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads, tx_pads=tx_pads,
rx_pads=rx_pads, rx_pads=rx_pads,
sys_clk_freq=sys_clk_freq) sys_clk_freq=self.clk_freq)
else: else:
raise ValueError raise ValueError
self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer( self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
self.transceiver.rtio_clk_freq) self.transceiver.rtio_clk_freq)
self.submodules.drtio = DRTIOSatellite( self.submodules.drtio = DRTIOSatellite(
self.transceiver, self.rx_synchronizer, rtio_channels) self.transceiver, self.rx_synchronizer, rtio_channels)
self.csr_devices.append("rx_synchronizer")
self.csr_devices.append("drtio")
self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
self.drtio.aux_controller.bus)
self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints( platform.add_false_path_constraints(
sys_clock_pads, platform.lookup_request("clk200"),
self.transceiver.txoutclk, self.transceiver.rxoutclk) self.transceiver.txoutclk, self.transceiver.rxoutclk)
def build(self, *args, **kwargs):
self.platform.build(self, *args, **kwargs)
def main(): def main():
parser = argparse.ArgumentParser(description="KC705 DRTIO satellite") parser = argparse.ArgumentParser(
parser.add_argument("--toolchain", default="vivado", description="ARTIQ with DRTIO on KC705 - Satellite")
help="FPGA toolchain to use: ise, vivado") builder_args(parser)
parser.add_argument("--output-dir", default="drtiosat_kc705", soc_kc705_args(parser)
help="output directory for generated "
"source files and binaries")
parser.add_argument("-c", "--config", default="simple_gbe", parser.add_argument("-c", "--config", default="simple_gbe",
help="configuration: simple_gbe/sawg_3g " help="configuration: simple_gbe/sawg_3g "
"(default: %(default)s)") "(default: %(default)s)")
@ -213,8 +220,10 @@ def main():
"(default: %(default)s)") "(default: %(default)s)")
args = parser.parse_args() args = parser.parse_args()
top = Satellite(args.config, args.medium, args.toolchain) soc = Satellite(args.config, args.medium, **soc_kc705_argdict(args))
top.build(build_dir=args.output_dir) builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__": if __name__ == "__main__":
main() main()