diff --git a/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py b/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py
index 1edd76f34..30645b876 100644
--- a/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py
+++ b/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py
@@ -1,7 +1,7 @@
 from math import ceil
 
 from migen import *
-from migen.genlib.cdc import MultiReg, PulseSynchronizer
+from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import WaitTimer