forked from M-Labs/artiq
parent
0e7e30d46e
commit
45cd438fb8
@ -15,6 +15,8 @@ Highlights:
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- Sampler: fixed ADC MU to Volt conversion factor for Sampler v2.2+.
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For earlier hardware versions, specify the hardware version in the device
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database file (e.g. ``"hw_rev": "v2.1"``) to use the correct conversion factor.
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- Almazny v1.2. It is incompatible with the legacy versions and is the default. To use legacy
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versions, specify ``almazny_hw_rev`` in the JSON description.
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- Metlino and Sayma support has been dropped due to complications with synchronous RTIO clocking.
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* CPU (on softcore platforms) and AXI bus (on Zynq) are now clocked synchronously with the RTIO
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clock, to facilitate implementation of local processing on DRTIO satellites, and to slightly
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178
artiq/coredevice/almazny.py
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178
artiq/coredevice/almazny.py
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@ -0,0 +1,178 @@
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from artiq.language.core import kernel, portable
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from numpy import int32
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# almazny-specific data
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ALMAZNY_LEGACY_REG_BASE = 0x0C
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ALMAZNY_LEGACY_OE_SHIFT = 12
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# higher SPI write divider to match almazny shift register timing
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# min SER time before SRCLK rise = 125ns
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# -> div=32 gives 125ns for data before clock rise
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# works at faster dividers too but could be less reliable
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ALMAZNY_LEGACY_SPIT_WR = 32
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class AlmaznyLegacy:
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"""
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Almazny (High frequency mezzanine board for Mirny)
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This applies to Almazny hardware v1.1 and earlier.
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Use :class:`artiq.coredevice.almazny.AlmaznyChannel` for Almazny v1.2 and later.
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:param host_mirny - Mirny device Almazny is connected to
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"""
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def __init__(self, dmgr, host_mirny):
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self.mirny_cpld = dmgr.get(host_mirny)
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self.att_mu = [0x3f] * 4
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self.channel_sw = [0] * 4
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self.output_enable = False
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@kernel
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def init(self):
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self.output_toggle(self.output_enable)
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@kernel
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def att_to_mu(self, att):
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"""
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Convert an attenuator setting in dB to machine units.
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:param att: attenuator setting in dB [0-31.5]
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:return: attenuator setting in machine units
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"""
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mu = round(att * 2.0)
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if mu > 63 or mu < 0:
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raise ValueError("Invalid Almazny attenuator settings!")
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return mu
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@kernel
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def mu_to_att(self, att_mu):
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"""
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Convert a digital attenuator setting to dB.
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:param att_mu: attenuator setting in machine units
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:return: attenuator setting in dB
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"""
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return att_mu / 2
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@kernel
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def set_att(self, channel, att, rf_switch=True):
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"""
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Sets attenuators on chosen shift register (channel).
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:param channel - index of the register [0-3]
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:param att_mu - attenuation setting in dBm [0-31.5]
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:param rf_switch - rf switch (bool)
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"""
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self.set_att_mu(channel, self.att_to_mu(att), rf_switch)
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@kernel
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def set_att_mu(self, channel, att_mu, rf_switch=True):
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"""
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Sets attenuators on chosen shift register (channel).
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:param channel - index of the register [0-3]
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:param att_mu - attenuation setting in machine units [0-63]
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:param rf_switch - rf switch (bool)
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"""
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self.channel_sw[channel] = 1 if rf_switch else 0
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self.att_mu[channel] = att_mu
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self._update_register(channel)
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@kernel
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def output_toggle(self, oe):
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"""
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Toggles output on all shift registers on or off.
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:param oe - toggle output enable (bool)
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"""
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self.output_enable = oe
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cfg_reg = self.mirny_cpld.read_reg(1)
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en = 1 if self.output_enable else 0
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delay(100 * us)
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new_reg = (en << ALMAZNY_LEGACY_OE_SHIFT) | (cfg_reg & 0x3FF)
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self.mirny_cpld.write_reg(1, new_reg)
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delay(100 * us)
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@kernel
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def _flip_mu_bits(self, mu):
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# in this form MSB is actually 0.5dB attenuator
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# unnatural for users, so we flip the six bits
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return (((mu & 0x01) << 5)
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| ((mu & 0x02) << 3)
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| ((mu & 0x04) << 1)
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| ((mu & 0x08) >> 1)
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| ((mu & 0x10) >> 3)
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| ((mu & 0x20) >> 5))
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@kernel
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def _update_register(self, ch):
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self.mirny_cpld.write_ext(
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ALMAZNY_LEGACY_REG_BASE + ch,
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8,
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self._flip_mu_bits(self.att_mu[ch]) | (self.channel_sw[ch] << 6),
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ALMAZNY_LEGACY_SPIT_WR
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)
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delay(100 * us)
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@kernel
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def _update_all_registers(self):
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for i in range(4):
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self._update_register(i)
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class AlmaznyChannel:
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"""
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One Almazny channel
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Almazny is a mezzanine for the Quad PLL RF source Mirny that exposes and
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controls the frequency-doubled outputs.
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This driver requires Almazny hardware revision v1.2 or later
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and Mirny CPLD gateware v0.3 or later.
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Use :class:`artiq.coredevice.almazny.AlmaznyLegacy` for Almazny hardware v1.1 and earlier.
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:param host_mirny: Mirny CPLD device name
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:param channel: channel index (0-3)
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"""
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def __init__(self, dmgr, host_mirny, channel):
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self.channel = channel
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self.mirny_cpld = dmgr.get(cpld_device)
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@portable
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def to_mu(self, att, enable, led):
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"""
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Convert an attenuation in dB, RF switch state and LED state to machine
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units.
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:param att: attenuator setting in dB (0-31.5)
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:param enable: RF switch state (bool)
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:param led: LED state (bool)
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:return: channel setting in machine units
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"""
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mu = int32(round(att * 2.))
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if mu >= 64 or mu < 0:
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raise ValueError("Attenuation out of range")
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# unfortunate hardware design: bit reverse
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mu = ((mu & 0x15) << 1) | ((mu >> 1) & 0x15)
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mu = ((mu & 0x03) << 4) | (mu & 0x0c) | ((mu >> 4) & 0x03)
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if enable:
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mu |= 1 << 6
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if led:
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mu |= 1 << 7
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return mu
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@kernel
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def set_mu(self, mu):
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"""
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Set channel state (machine units).
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:param mu: channel state in machine units.
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"""
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self.mirny_cpld.write_ext(
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addr=0xc + self.channel, length=8, data=mu, ext_div=32)
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@kernel
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def set(self, att, enable, led=False):
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"""
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Set attenuation, RF switch, and LED state (SI units).
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:param att: attenuator setting in dB (0-31.5)
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:param enable: RF switch state (bool)
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:param led: LED state (bool)
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"""
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self.set_mu(self.to_mu(att, enable, led))
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@ -512,6 +512,11 @@
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"almazny": {
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"type": "boolean",
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"default": false
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},
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"almazny_hw_rev": {
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"type": "string",
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"pattern": "^v[0-9]+\\.[0-9]+",
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"default": "v1.2"
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}
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},
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"required": ["ports"]
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@ -31,16 +31,6 @@ WE = 1 << 24
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# supported CPLD code version
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PROTO_REV_MATCH = 0x0
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# almazny-specific data
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ALMAZNY_REG_BASE = 0x0C
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ALMAZNY_OE_SHIFT = 12
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# higher SPI write divider to match almazny shift register timing
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# min SER time before SRCLK rise = 125ns
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# -> div=32 gives 125ns for data before clock rise
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# works at faster dividers too but could be less reliable
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ALMAZNY_SPIT_WR = 32
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class Mirny:
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"""
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@ -177,106 +167,3 @@ class Mirny:
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if length < 32:
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data <<= 32 - length
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self.bus.write(data)
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class Almazny:
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"""
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Almazny (High frequency mezzanine board for Mirny)
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:param host_mirny - Mirny device Almazny is connected to
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"""
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def __init__(self, dmgr, host_mirny):
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self.mirny_cpld = dmgr.get(host_mirny)
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self.att_mu = [0x3f] * 4
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self.channel_sw = [0] * 4
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self.output_enable = False
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@kernel
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def init(self):
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self.output_toggle(self.output_enable)
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@kernel
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def att_to_mu(self, att):
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"""
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Convert an attenuator setting in dB to machine units.
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:param att: attenuator setting in dB [0-31.5]
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:return: attenuator setting in machine units
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"""
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mu = round(att * 2.0)
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if mu > 63 or mu < 0:
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raise ValueError("Invalid Almazny attenuator settings!")
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return mu
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@kernel
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def mu_to_att(self, att_mu):
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"""
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Convert a digital attenuator setting to dB.
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:param att_mu: attenuator setting in machine units
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:return: attenuator setting in dB
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"""
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return att_mu / 2
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@kernel
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def set_att(self, channel, att, rf_switch=True):
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"""
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Sets attenuators on chosen shift register (channel).
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:param channel - index of the register [0-3]
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:param att_mu - attenuation setting in dBm [0-31.5]
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:param rf_switch - rf switch (bool)
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"""
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self.set_att_mu(channel, self.att_to_mu(att), rf_switch)
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@kernel
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def set_att_mu(self, channel, att_mu, rf_switch=True):
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"""
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Sets attenuators on chosen shift register (channel).
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:param channel - index of the register [0-3]
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:param att_mu - attenuation setting in machine units [0-63]
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:param rf_switch - rf switch (bool)
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"""
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self.channel_sw[channel] = 1 if rf_switch else 0
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self.att_mu[channel] = att_mu
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self._update_register(channel)
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@kernel
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def output_toggle(self, oe):
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"""
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Toggles output on all shift registers on or off.
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:param oe - toggle output enable (bool)
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"""
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self.output_enable = oe
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cfg_reg = self.mirny_cpld.read_reg(1)
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en = 1 if self.output_enable else 0
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delay(100 * us)
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new_reg = (en << ALMAZNY_OE_SHIFT) | (cfg_reg & 0x3FF)
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self.mirny_cpld.write_reg(1, new_reg)
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delay(100 * us)
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@kernel
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def _flip_mu_bits(self, mu):
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# in this form MSB is actually 0.5dB attenuator
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# unnatural for users, so we flip the six bits
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return (((mu & 0x01) << 5)
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| ((mu & 0x02) << 3)
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| ((mu & 0x04) << 1)
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| ((mu & 0x08) >> 1)
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| ((mu & 0x10) >> 3)
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| ((mu & 0x20) >> 5))
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@kernel
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def _update_register(self, ch):
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self.mirny_cpld.write_ext(
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ALMAZNY_REG_BASE + ch,
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8,
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self._flip_mu_bits(self.att_mu[ch]) | (self.channel_sw[ch] << 6),
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ALMAZNY_SPIT_WR
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)
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delay(100 * us)
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@kernel
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def _update_all_registers(self):
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for i in range(4):
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self._update_register(i)
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@ -287,6 +287,7 @@ class PeripheralManager:
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return next(channel)
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def process_mirny(self, rtio_offset, peripheral):
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legacy_almazny = ("v1.0", "v1.1")
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mirny_name = self.get_name("mirny")
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channel = count(0)
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self.gen("""
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@ -326,6 +327,20 @@ class PeripheralManager:
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name=mirny_name,
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mchn=i)
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if peripheral["almazny"] and peripheral["almazny_hw_rev"] not in legacy_almazny:
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self.gen("""
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device_db["{name}_almazny{i}"] = {{
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"type": "local",
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"module": "artiq.coredevice.almazny",
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"class": "AlmaznyChannel",
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"arguments": {{
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"cpld_device": "{name}_cpld",
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"channel": {i},
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}},
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}}""",
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name=mirny_name,
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i=i)
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clk_sel = peripheral["clk_sel"]
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if isinstance(peripheral["clk_sel"], str):
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clk_sel = '"' + peripheral["clk_sel"] + '"'
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@ -343,13 +358,12 @@ class PeripheralManager:
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name=mirny_name,
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refclk=peripheral["refclk"],
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clk_sel=clk_sel)
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almazny = peripheral.get("almazny", False)
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if almazny:
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if peripheral["almazny"] and peripheral["almazny_hw_rev"] in legacy_almazny:
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self.gen("""
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device_db["{name}_almazny"] = {{
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"type": "local",
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"module": "artiq.coredevice.mirny",
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"class": "Almazny",
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"module": "artiq.coredevice.almazny",
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"class": "AlmaznyLegacy",
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"arguments": {{
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"host_mirny": "{name}_cpld",
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}},
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@ -98,7 +98,7 @@ class SinaraTester(EnvExperiment):
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self.suservos[name] = self.get_device(name)
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elif (module, cls) == ("artiq.coredevice.suservo", "Channel"):
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self.suschannels[name] = self.get_device(name)
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elif (module, cls) == ("artiq.coredevice.mirny", "Almazny"):
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elif (module, cls) == ("artiq.coredevice.almazny", "AlmaznyLegacy"):
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self.almaznys[name] = self.get_device(name)
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# Remove Urukul, Sampler, Zotino and Mirny control signals
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@ -92,6 +92,12 @@ RF generation drivers
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.. automodule:: artiq.coredevice.mirny
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:members:
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:mod:`artiq.coredevice.almazny` module
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++++++++++++++++++++++++++++++++++++++
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.. automodule:: artiq.coredevice.almazny
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:members:
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:mod:`artiq.coredevice.adf5356` module
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+++++++++++++++++++++++++++++++++++++++
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Reference in New Issue
Block a user