forked from M-Labs/artiq
runtime/mailbox: remove flush of L2 cache (L2 cache is now shared between CPUs)
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@ -29,22 +29,8 @@ static void _flush_cpu_dcache(void)
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mtspr(SPR_DCBIR, i);
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}
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/* TODO: do not use L2 cache in AMP systems */
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static void _flush_l2_cache(void)
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{
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unsigned int i;
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register unsigned int addr;
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register unsigned int dummy;
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for(i=0;i<2*8192/4;i++) {
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addr = 0x40000000 + i*4;
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__asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
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}
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}
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void mailbox_send(void *ptr)
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{
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_flush_l2_cache();
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last_transmission = (unsigned int)ptr;
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KERNELCPU_MAILBOX = last_transmission;
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}
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@ -72,7 +58,6 @@ void *mailbox_receive(void)
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return NULL;
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else {
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if(r) {
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_flush_l2_cache();
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_flush_cpu_dcache();
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}
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return (void *)r;
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