From 44969b03ad303a1efbdc7262867f54df5ebf6f28 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 15 Aug 2019 15:55:13 +0800 Subject: [PATCH] wrpll/thls: rework instruction decoding --- artiq/gateware/wrpll/thls.py | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/artiq/gateware/wrpll/thls.py b/artiq/gateware/wrpll/thls.py index ba2dde7f6..0cc244806 100644 --- a/artiq/gateware/wrpll/thls.py +++ b/artiq/gateware/wrpll/thls.py @@ -45,17 +45,19 @@ class SubIsn(Isn): class MulShiftIsn(Isn): opcode = 3 +# opcode = 4: MulShift with alternate shift + class CopyIsn(Isn): - opcode = 4 + opcode = 7 class InputIsn(Isn): - opcode = 5 + opcode = 8 class OutputIsn(Isn): - opcode = 6 + opcode = 9 class EndIsn(Isn): - opcode = 7 + opcode = 10 class ASTCompiler: @@ -139,7 +141,7 @@ class Processor: self.multiplier_shifts = [] self.program_rom_size = None self.data_ram_size = None - self.opcode_bits = 3 + self.opcode_bits = 4 self.reg_bits = None def get_instruction_latency(self, isn): @@ -472,8 +474,7 @@ class ProcessorImpl(Module): units = [nop, adder, subtractor, multiplier, copier, inu, outu] self.submodules += units - for n, unit in enumerate(units): - self.sync += unit.stb_i.eq(pc_en & (opcode == n)) + for unit in units: self.comb += [ unit.i0.eq(data_read_port0.dat_r), unit.i1.eq(data_read_port1.dat_r), @@ -483,6 +484,19 @@ class ProcessorImpl(Module): ) ] + decode_table = [ + (NopIsn.opcode, nop), + (AddIsn.opcode, adder), + (SubIsn.opcode, subtractor), + (MulShiftIsn.opcode, multiplier), + (MulShiftIsn.opcode + 1, multiplier), + (CopyIsn.opcode, copier), + (InputIsn.opcode, inu), + (OutputIsn.opcode, outu) + ] + for allocated_opcode, unit in decode_table: + self.sync += unit.stb_i.eq(pc_en & (opcode == allocated_opcode)) + fsm = FSM() self.submodules += fsm fsm.act("IDLE",