srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma: add RTM configuration port.

This commit is contained in:
whitequark 2018-01-16 07:28:00 +00:00
parent 702c35821b
commit 444b901dbe
2 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -7,6 +7,7 @@ from collections import namedtuple
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from misoc.cores.slave_fpga import SlaveFPGA
from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
from misoc.integration.builder import builder_args, builder_argdict from misoc.integration.builder import builder_args, builder_argdict
from misoc.interconnect import stream from misoc.interconnect import stream
@ -147,6 +148,11 @@ class Standalone(MiniSoC, AMPSoC):
serial_rtm.tx.eq(serial_1.rx) serial_rtm.tx.eq(serial_1.rx)
] ]
# RTM bitstream upload
rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
self.csr_devices.append("rtm_fpga_cfg")
# AMC/RTM serwb # AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=2) serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=2)
self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk) self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)

4
conda/artiq-dev/meta.yaml
View File

@ -14,8 +14,8 @@ requirements:
run: run:
- python >=3.5.3,<3.6 - python >=3.5.3,<3.6
- setuptools 33.1.1 - setuptools 33.1.1
- migen 0.6.dev py35_64+gitc6ffa44 - migen 0.6 py35_2+git61a055f
- misoc 0.8 py35_14+git97f1b8a6 - misoc 0.8 py35_15+gitc5082e52
- jesd204b 0.4 - jesd204b 0.4
- microscope - microscope
- binutils-or1k-linux >=2.27 - binutils-or1k-linux >=2.27