forked from M-Labs/artiq
README_PHASER: integrate into board port docs
* rewrite setup commands for usage of artiq-dev metapackage * integrate with rest of installation documentation * move contents of README_PHASER to core_device.rst * closes #815
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ARTIQ Phaser
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============
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ARTIQ contains a proof-of-concept design of a GHz-datarate, multi-channel, interpolating, multi-tone, direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels.
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Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Generator project. See https://github.com/m-labs/sinara and https://github.com/m-labs/artiq-hardware.
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*Features*:
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* up to 4 channels
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* up to 500 MHz data rate per channel (KC705 limitation)
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* up to 8x interpolation to 2.4 GHz DAC sample rate
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* Real-time sample-coherent control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands
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* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel support
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* All SPI registers and register bits exposed as human readable names
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* Parametrized JESD204B core (also capable of operation with eight lanes)
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* The code can be reconfigured. Possible example configurations are: support 2 channels at 1 GHz datarate, support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz). Please contact M-Labs if you need help with this.
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The hardware required is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise sample rate reference clock.
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This work was supported by the Army Research Lab and the University of Maryland.
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The code that was developed for this project is located in several repositories:
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* In ARTIQ, the SAWG and Phaser code: https://github.com/m-labs/artiq
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* The Migen/MiSoC JESD204B core: https://github.com/m-labs/jesd204b
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Installation
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------------
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These installation instructions are a short form of those in the ARTIQ manual.
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Please refer to and follow the ARTIQ manual for more details:
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https://m-labs.hk/artiq/manual-master/index.html
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* Set up a new conda environment and activate it.
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* Install the standard ARTIQ runtime/install dependencies.
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See ``conda/artiq/meta.yaml`` for a list.
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They are all packaged as conda packages in ``m-labs/main``.
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* Install the standard ARTIQ build dependencies.
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They are all available as conda packages in m-labs/main or m-labs/dev for linux-64:
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- migen
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- misoc
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- jesd204b
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- llvm-or1k
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- rust-core-or1k
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- cargo
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- binutils-or1k-linux
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* Install a recent version of Vivado (tested and developed with 2016.2).
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* Do a checkout of ARTIQ: ::
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mkdir ~/src
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cd ~/src
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git clone --recursive https://github.com/m-labs/artiq.git
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cd ../artiq
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python setup.py develop
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Setup
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-----
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* Setup the KC705 (jumpers, etc.) observing the ARTIQ manual.
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VADJ does not need to be changed.
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* On the AD9154-FMC-EBZ put jumpers:
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- on XP1, between pin 5 and 6 (will keep the PIC in reset)
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- on JP3 (will force output enable on FXLA108)
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* Compile the ARTIQ Phaser bitstream, bios, and runtime (c.f. ARTIQ manual): ::
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python -m artiq.gateware.targets.phaser
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* From time to time and on request there may be pre-built binaries in the
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``artiq-kc705-phaser`` package on the M-Labs conda package label.
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* Generate an ARTIQ configuration flash image with MAC and IP address (see the
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documentation for ``artiq_mkfs``). Name it ``phaser_config.bin``.
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* Run the following OpenOCD command to flash the ARTIQ phaser design: ::
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openocd -f board/kc705.cfg -c "init; jtagspi_init 0 bscan_spi_xc7k325t.bit; jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000; jtagspi_program misoc_phaser_kc705/software/bios/bios.bin 0xaf0000; jtagspi_program misoc_phaser_kc705/software/runtime/runtime.fbi 0xb00000;jtagspi_program phaser_config.bin 0xb80000; xc7_program xc7.tap; exit"
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The proxy bitstream ``bscan_spi_xc7k325t.bit`` can be found at https://github.com/jordens/bscan_spi_bitstreams or in any ARTIQ conda package for the KC705.
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See the source code of ``artiq_flash.py`` from ARTIQ for more details.
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If you are using the OpenOCD Conda package:
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* locate the OpenOCD scripts directory with: ``python3 -c "import artiq.frontend.artiq_flash as af; print(af.scripts_path)"``
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* add ``-s <scripts directory>`` to the OpenOCD command line.
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* Refer to the ARTIQ documentation to configure an IP address and other settings for the transmitter device.
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If the board was running stock ARTIQ before, the settings will be kept.
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* A 300 MHz clock of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1. The input is 50 Ohm terminated. The RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
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* The RTIO coarse clock (the rate of the RTIO timestamp counter) is 150
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MHz. The RTIO ``ref_period`` is 1/150 MHz = 5ns/6. The RTIO ``ref_multiplier`` is ``8``. C.f. ``device_db.py`` for both variables. The JED204B DAC data rate and DAC device clock are both 300 MHz. The JESD204B line rate is 6 GHz.
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* Configure an oscilloscope to trigger at 0.5 V on rising edge of ttl_sma (user_gpio_n on the KC705 board). Monitor DAC0 (J17) on the oscilloscope set for 100 mV/div and 200 ns/div.
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* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``. ::
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cd artiq/examples/phaser
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* Edit ``device_db.py`` to match the hostname or IP address of the core device.
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* Use ``ping`` and ``flterm`` to verify that the core device starts up and boots correctly.
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Usage
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-----
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* Run ``artiq_run repository/demo.py`` for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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* Run ``artiq_run repository/demo_2tone.py`` for an example that emits a shaped two-tone pulse.
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* Implement your own experiments using the SAWG channels.
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* Verify clock stability between the sample rate reference clock and the DAC outputs.
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@ -133,11 +133,73 @@ To avoid I/O contention, the startup kernel should first program the TCA6424A ex
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See :mod:`artiq.coredevice.i2c` for more details.
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.. _phaser:
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Phaser
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++++++
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The Phaser adapter is an AD9154-FMC-EBZ, a 4 channel 2.4 GHz DAC on an FMC HPC card.
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Phaser is a proof-of-concept design of a GHz-datarate, multi-channel, interpolating, multi-tone, direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels.
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Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Generator project. See https://github.com/m-labs/sinara.
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*Features*:
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* up to 4 channels
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* up to 500 MHz data rate per channel (KC705 limitation)
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* up to 8x interpolation to 2.4 GHz DAC sample rate
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* Real-time sample-coherent control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands
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* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel support
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* All SPI registers and register bits exposed as human readable names
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* Parametrized JESD204B core (also capable of operation with eight lanes)
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* The code can be reconfigured. Possible example configurations are: support 2 channels at 1 GHz datarate, support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz). Please contact M-Labs if you need help with this.
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The hardware required is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise sample rate reference clock.
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This work was supported by the Army Research Lab and the University of Maryland.
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Installation
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............
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These installation instructions are a short form of those in the ARTIQ manual.
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* See the chapter on setting up a :ref:`development environment <develop-from-conda>`.
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* When compiling the binaries, use the ``phaser`` target:::
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$ python -m artiq.gateware.targets.phaser
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* From time to time and on request there may be pre-built binaries in the
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``artiq-kc705-phaser`` package on the M-Labs conda package label.
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Setup
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.....
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* Setup the KC705 (jumpers, etc.) observing the ARTIQ manual. VADJ does not need to be changed.
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* On the AD9154-FMC-EBZ put jumpers:
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- on XP1, between pin 5 and 6 (will keep the PIC in reset)
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- on JP3 (will force output enable on FXLA108)
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* Refer to the ARTIQ documentation to configure the MAC and IP addresses and other settings. If the board was running stock ARTIQ before, the settings will be kept.
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* A 300 MHz clock of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1. The input is 50 Ohm terminated. The RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
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* The RTIO coarse clock (the rate of the RTIO timestamp counter) is 150 MHz. The RTIO ``ref_period`` is 1/150 MHz = 5ns/6. The RTIO ``ref_multiplier`` is ``8``. C.f. ``device_db.py`` for both variables. The JED204B DAC data rate and DAC device clock are both 300 MHz. The JESD204B line rate is 6 GHz.
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* Configure an oscilloscope to trigger at 0.5 V on rising edge of ttl_sma (user_gpio_n on the KC705 board). Monitor DAC0 (J17) on the oscilloscope set for 100 mV/div and 200 ns/div.
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* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``. ::
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cd artiq/examples/phaser
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* Edit ``device_db.py`` to match the hostname or IP address of the core device.
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* Use ``ping`` and ``flterm`` to verify that the core device starts up and boots correctly.
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Usage
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.....
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* Run ``artiq_run repository/demo.py`` for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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* Run ``artiq_run repository/demo_2tone.py`` for an example that emits a shaped two-tone pulse.
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* Implement your own experiments using the SAWG channels.
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* Verify clock stability between the sample rate reference clock and the DAC outputs.
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RTIO channels
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.............
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+--------------+------------+--------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+==============+
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