From 439d2bf2bc3b236193a05e471f4d2c8863f30d6a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 17 Apr 2018 19:22:09 +0200 Subject: [PATCH] sayma/serwb: adapt, full reset of rtm on link reset --- artiq/gateware/targets/sayma_amc.py | 4 ++-- artiq/gateware/targets/sayma_rtm.py | 16 ++++++++++------ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 896a00ae7..db2387f73 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -170,11 +170,11 @@ class Standalone(MiniSoC, AMPSoC): # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") - serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master", phy_width=4) + serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master") self.submodules.serwb_phy_amc = serwb_phy_amc self.csr_devices.append("serwb_phy_amc") - serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True) + serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave") self.submodules += serwb_core self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 22e2580fb..07199320b 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -26,6 +26,7 @@ class CRG(Module): self.clock_domains.cd_clk200 = ClockDomain() self.serwb_refclk = Signal() + self.serwb_reset = Signal() pll_locked = Signal() pll_fb = Signal() @@ -53,9 +54,9 @@ class CRG(Module): Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - AsyncResetSynchronizer(self.cd_sys4x, ~pll_locked), - AsyncResetSynchronizer(self.cd_clk200, ~pll_locked) + AsyncResetSynchronizer(self.cd_sys, ~pll_locked | self.serwb_reset), + AsyncResetSynchronizer(self.cd_sys4x, ~pll_locked | self.serwb_reset), + AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | self.serwb_reset) ] reset_counter = Signal(4, reset=15) @@ -156,12 +157,15 @@ class SaymaRTM(Module): # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") platform.add_period_constraint(serwb_pads.clk_p, 10.) - serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave", phy_width=4) + serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave") self.submodules.serwb_phy_rtm = serwb_phy_rtm - self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk) + self.comb += [ + self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk), + self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset) + ] csr_devices.append("serwb_phy_rtm") - serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True) + serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master") self.submodules += serwb_core # process CSR devices and connect them to serwb