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rtio: describe rio and rio_phy domains a bit more

This commit is contained in:
Robert Jördens 2017-06-17 12:21:07 +02:00
parent 219dfd8984
commit 424b2bfbd8
1 changed files with 8 additions and 0 deletions
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8
artiq/gateware/rtio/core.py
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@ -298,6 +298,14 @@ class Core(Module, AutoCSR):
# Clocking/Reset # Clocking/Reset
# Create rsys, rio and rio_phy domains based on sys and rtio # Create rsys, rio and rio_phy domains based on sys and rtio
# with reset controlled by CRI. # with reset controlled by CRI.
#
# The `rio` CD contains logic that is reset with `core.reset()`.
# That's state that could unduly affect subsequent experiments,
# i.e. input overflows caused by input gates left open, FIFO events far
# in the future blocking the experiment, pending RTIO or
# wishbone bus transactions, etc.
# The `rio_phy` CD contains state that is maintained across
# `core.reset()`, i.e. TTL output state, OE, DDS state.
cmd_reset = Signal(reset=1) cmd_reset = Signal(reset=1)
cmd_reset_phy = Signal(reset=1) cmd_reset_phy = Signal(reset=1)
self.sync += [ self.sync += [