forked from M-Labs/artiq
dsp: move test tools
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424a1f8f4e
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@ -4,32 +4,6 @@ from functools import reduce
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from migen import *
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from migen import *
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def set_dict(e, **k):
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for k, v in k.items():
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if isinstance(v, dict):
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yield from set_dict(getattr(e, k), **v)
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else:
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yield getattr(e, k).eq(v)
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def xfer(dut, **kw):
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ep = []
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for e, v in kw.items():
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e = getattr(dut, e)
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yield from set_dict(e, **v)
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ep.append(e)
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for e in ep:
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yield e.stb.eq(1)
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while ep:
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yield
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for e in ep[:]:
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if hasattr(e, "busy") and (yield e.busy):
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raise ValueError(e, "busy")
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if not hasattr(e, "ack") or (yield e.ack):
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yield e.stb.eq(0)
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ep.remove(e)
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class Delay(Module):
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class Delay(Module):
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def __init__(self, i, delay, o=None):
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def __init__(self, i, delay, o=None):
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if isinstance(i, (int, tuple)):
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if isinstance(i, (int, tuple)):
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@ -73,22 +47,3 @@ class SatAddMixin:
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)
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)
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]
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]
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return s0
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return s0
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def szip(*iters):
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active = {it: None for it in iters}
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while active:
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for it in list(active):
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while True:
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try:
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val = it.send(active[it])
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except StopIteration:
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del active[it]
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break
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if val is None:
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break
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else:
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active[it] = (yield val)
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val = (yield None)
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for it in active:
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active[it] = val
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@ -4,7 +4,7 @@ from migen import *
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from migen.fhdl.verilog import convert
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp.accu import Accu, PhasedAccu
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from artiq.gateware.dsp.accu import Accu, PhasedAccu
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from artiq.gateware.dsp.tools import xfer
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from .tools import xfer
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def read(o, n):
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def read(o, n):
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@ -4,7 +4,7 @@ from migen import *
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from migen.fhdl.verilog import convert
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp.sawg import DDSFast
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from artiq.gateware.dsp.sawg import DDSFast
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from artiq.gateware.dsp.tools import xfer
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from .tools import xfer
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def _test_gen_dds(dut, o):
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def _test_gen_dds(dut, o):
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@ -4,7 +4,7 @@ from migen import *
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from migen.fhdl.verilog import convert
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from migen.fhdl.verilog import convert
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from artiq.gateware.rtio.phy.sawg import Channel
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from artiq.gateware.rtio.phy.sawg import Channel
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from artiq.gateware.dsp.tools import xfer, szip
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from .tools import xfer, szip
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def rtio_xfer(dut, **kwargs):
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def rtio_xfer(dut, **kwargs):
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@ -4,7 +4,7 @@ from migen import *
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from migen.fhdl.verilog import convert
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp.spline import Spline
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from artiq.gateware.dsp.spline import Spline
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from artiq.gateware.dsp.tools import xfer
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from .tools import xfer
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def _test_gen_spline(dut, o):
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def _test_gen_spline(dut, o):
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@ -0,0 +1,43 @@
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def set_dict(e, **k):
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for k, v in k.items():
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if isinstance(v, dict):
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yield from set_dict(getattr(e, k), **v)
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else:
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yield getattr(e, k).eq(v)
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def xfer(dut, **kw):
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ep = []
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for e, v in kw.items():
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e = getattr(dut, e)
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yield from set_dict(e, **v)
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ep.append(e)
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for e in ep:
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yield e.stb.eq(1)
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while ep:
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yield
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for e in ep[:]:
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if hasattr(e, "busy") and (yield e.busy):
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raise ValueError(e, "busy")
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if not hasattr(e, "ack") or (yield e.ack):
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yield e.stb.eq(0)
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ep.remove(e)
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def szip(*iters):
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active = {it: None for it in iters}
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while active:
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for it in list(active):
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while True:
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try:
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val = it.send(active[it])
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except StopIteration:
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del active[it]
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break
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if val is None:
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break
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else:
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active[it] = (yield val)
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val = (yield None)
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for it in active:
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active[it] = val
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