forked from M-Labs/artiq
rtio/sed: latency compensation
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e430d04d3f
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4112e403de
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@ -31,7 +31,9 @@ class SED(Module):
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self.submodules.lane_dist = lane_dist_cdr(
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LaneDistributor(lane_count, seqn_width,
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layouts.fifo_payload(channels), glbl_fine_ts_width,
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layouts.fifo_payload(channels),
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[channel.interface.o.delay for channel in channels],
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glbl_fine_ts_width,
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enable_spread=enable_spread,
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quash_channels=quash_channels,
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interface=interface))
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@ -13,7 +13,8 @@ __all__ = ["LaneDistributor"]
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# 3. check status
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class LaneDistributor(Module):
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def __init__(self, lane_count, seqn_width, layout_payload, glbl_fine_ts_width,
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def __init__(self, lane_count, seqn_width, layout_payload,
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compensation, glbl_fine_ts_width,
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enable_spread=True, quash_channels=[], interface=None):
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if lane_count & (lane_count - 1):
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raise NotImplementedError("lane count must be a power of 2")
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@ -53,27 +54,20 @@ class LaneDistributor(Module):
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self.comb += lio.payload.data.eq(self.cri.o_data)
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# when timestamp and channel arrive in cycle #1, prepare computations
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coarse_timestamp = Signal(64-glbl_fine_ts_width)
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us_timestamp_width = 64 - glbl_fine_ts_width
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coarse_timestamp = Signal(us_timestamp_width)
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self.comb += coarse_timestamp.eq(self.cri.timestamp[glbl_fine_ts_width:])
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timestamp_above_min = Signal()
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timestamp_above_laneA_min = Signal()
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timestamp_above_laneB_min = Signal()
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force_laneB = Signal()
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use_laneB = Signal()
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use_lanen = Signal(max=lane_count)
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min_minus_timestamp = Signal((us_timestamp_width + 1, True))
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laneAmin_minus_timestamp = Signal((us_timestamp_width + 1, True))
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laneBmin_minus_timestamp = Signal((us_timestamp_width + 1, True))
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last_minus_timestamp = Signal((us_timestamp_width + 1, True))
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current_lane_plus_one = Signal(max=lane_count)
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self.comb += current_lane_plus_one.eq(current_lane + 1)
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self.sync += [
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timestamp_above_min.eq(coarse_timestamp > self.minimum_coarse_timestamp),
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timestamp_above_laneA_min.eq(coarse_timestamp > last_lane_coarse_timestamps[current_lane]),
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timestamp_above_laneB_min.eq(coarse_timestamp > last_lane_coarse_timestamps[current_lane_plus_one]),
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If(force_laneB | (coarse_timestamp <= last_coarse_timestamp),
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use_lanen.eq(current_lane + 1),
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use_laneB.eq(1)
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).Else(
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use_lanen.eq(current_lane),
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use_laneB.eq(0)
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)
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min_minus_timestamp.eq(self.minimum_coarse_timestamp - coarse_timestamp),
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laneAmin_minus_timestamp.eq(last_lane_coarse_timestamps[current_lane] - coarse_timestamp),
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laneBmin_minus_timestamp.eq(last_lane_coarse_timestamps[current_lane_plus_one] - coarse_timestamp),
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last_minus_timestamp.eq(last_coarse_timestamp - coarse_timestamp)
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]
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quash = Signal()
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@ -81,12 +75,36 @@ class LaneDistributor(Module):
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for channel in quash_channels:
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self.sync += If(self.cri.chan_sel[:16] == channel, quash.eq(1))
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latency_compensation = Memory(14, len(compensation), init=compensation)
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latency_compensation_port = latency_compensation.get_port()
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self.specials += latency_compensation, latency_compensation_port
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self.comb += latency_compensation_port.adr.eq(self.cri.chan_sel[:16])
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# cycle #2, write
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compensation = latency_compensation_port.dat_r
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timestamp_above_min = Signal()
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timestamp_above_laneA_min = Signal()
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timestamp_above_laneB_min = Signal()
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timestamp_above_lane_min = Signal()
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force_laneB = Signal()
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use_laneB = Signal()
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use_lanen = Signal(max=lane_count)
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do_write = Signal()
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do_underflow = Signal()
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do_sequence_error = Signal()
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self.comb += [
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timestamp_above_min.eq(min_minus_timestamp - compensation < 0),
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timestamp_above_laneA_min.eq(laneAmin_minus_timestamp - compensation < 0),
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timestamp_above_laneB_min.eq(laneBmin_minus_timestamp - compensation < 0),
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If(force_laneB | (last_minus_timestamp - compensation >= 0),
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use_lanen.eq(current_lane + 1),
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use_laneB.eq(1)
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).Else(
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use_lanen.eq(current_lane),
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use_laneB.eq(0)
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),
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timestamp_above_lane_min.eq(Mux(use_laneB, timestamp_above_laneB_min, timestamp_above_laneA_min)),
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If(~quash,
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do_write.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & timestamp_above_lane_min),
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@ -95,14 +113,18 @@ class LaneDistributor(Module):
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),
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Array(lio.we for lio in self.output)[use_lanen].eq(do_write)
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]
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compensated_timestamp = Signal(64)
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self.comb += compensated_timestamp.eq(self.cri.timestamp + (compensation << glbl_fine_ts_width))
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self.sync += [
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If(do_write,
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If(use_laneB, current_lane.eq(current_lane + 1)),
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last_coarse_timestamp.eq(coarse_timestamp),
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last_lane_coarse_timestamps[use_lanen].eq(coarse_timestamp),
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last_coarse_timestamp.eq(compensated_timestamp[glbl_fine_ts_width:]),
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last_lane_coarse_timestamps[use_lanen].eq(compensated_timestamp[glbl_fine_ts_width:]),
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seqn.eq(seqn + 1),
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)
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]
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for lio in self.output:
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self.comb += lio.payload.timestamp.eq(compensated_timestamp)
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# cycle #3, read status
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current_lane_writable = Signal()
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@ -10,7 +10,8 @@ LANE_COUNT = 8
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def simulate(input_events, wait=True):
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dut = lane_distributor.LaneDistributor(LANE_COUNT, 8, [("channel", 8), ("timestamp", 32)], 3)
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dut = lane_distributor.LaneDistributor(LANE_COUNT, 8, [("channel", 8), ("timestamp", 32)],
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[0]*256, 3)
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output = []
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access_results = []
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