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analyses.domination: consider unreachable blocks dominated by any other. 

As a result, the dominator tree can now process arbitrary (reducible)
CFGs and we do not run DCE before analyses, risking loss of
correspondence to the AST, which would arbitrarily silence analyses.
This commit is contained in:
whitequark 2015-12-18 16:39:42 +08:00
parent 59a3ea4f15
commit 3fbee2707b
2 changed files with 9 additions and 4 deletions
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8
artiq/compiler/analyses/domination.py
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@ -74,7 +74,11 @@ class GenericDominatorTree:
return self._block_of_name[self._doms[self._name_of_block[block]]] return self._block_of_name[self._doms[self._name_of_block[block]]]
def dominators(self, block): def dominators(self, block):
yield block # Blocks that are statically unreachable from entry are considered
# dominated by every other block.
if block not in self._name_of_block:
yield from self._block_of_name
return
block_name = self._name_of_block[block] block_name = self._name_of_block[block]
while block_name != self._doms[block_name]: while block_name != self._doms[block_name]:
@ -103,6 +107,8 @@ class DominatorTree(GenericDominatorTree):
def _prev_block_names(self, block_name): def _prev_block_names(self, block_name):
for block in self._block_of_name[block_name].predecessors(): for block in self._block_of_name[block_name].predecessors():
# Only return predecessors that are statically reachable from entry.
if block in self._name_of_block:
yield self._name_of_block[block] yield self._name_of_block[block]
class PostDominatorTree(GenericDominatorTree): class PostDominatorTree(GenericDominatorTree):

3
artiq/compiler/module.py
View File

@ -70,10 +70,9 @@ class Module:
devirtualization.visit(src.typedtree) devirtualization.visit(src.typedtree)
self.artiq_ir = artiq_ir_generator.visit(src.typedtree) self.artiq_ir = artiq_ir_generator.visit(src.typedtree)
artiq_ir_generator.annotate_calls(devirtualization) artiq_ir_generator.annotate_calls(devirtualization)
dead_code_eliminator.process(self.artiq_ir)
local_access_validator.process(self.artiq_ir) local_access_validator.process(self.artiq_ir)
interleaver.process(self.artiq_ir)
dead_code_eliminator.process(self.artiq_ir) dead_code_eliminator.process(self.artiq_ir)
interleaver.process(self.artiq_ir)
def build_llvm_ir(self, target): def build_llvm_ir(self, target):
"""Compile the module to LLVM IR for the specified target.""" """Compile the module to LLVM IR for the specified target."""