srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sawg: register pre-hbf adder

This commit is contained in:
Robert Jördens 2017-06-13 18:15:44 +02:00
parent e229edd5d5
commit 3f37870e25
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/dsp/sawg.py
View File

@ -150,7 +150,7 @@ class Channel(Module, SatAddMixin):
self.u.latency += 1 self.u.latency += 1
b.p.latency += 2 b.p.latency += 2
b.f.latency += 2 b.f.latency += 2
a_latency_delta = hbf[0].latency + b.latency + 2 a_latency_delta = hbf[0].latency + b.latency + 3
for a in a1, a2: for a in a1, a2:
a.a.latency += a_latency_delta a.a.latency += a_latency_delta
a.p.latency += a_latency_delta a.p.latency += a_latency_delta
@ -185,7 +185,7 @@ class Channel(Module, SatAddMixin):
# correct pre-DUC limiter by cordic gain # correct pre-DUC limiter by cordic gain
v = cfg.limits[i][j].reset.value v = cfg.limits[i][j].reset.value
cfg.limits[i][j].reset.value = int(v / b.gain) cfg.limits[i][j].reset.value = int(v / b.gain)
self.comb += [ self.sync += [
hbf[0].i.eq(a1.xo[0] + a2.xo[0]), hbf[0].i.eq(a1.xo[0] + a2.xo[0]),
hbf[1].i.eq(a1.yo[0] + a2.yo[0]) hbf[1].i.eq(a1.yo[0] + a2.yo[0])
] ]