From 3f076bf79bbc5abc18fef53d5b26288fea89fb78 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 16 Oct 2020 22:05:20 +0800 Subject: [PATCH] wrpll: fix mulshift --- artiq/gateware/drtio/wrpll/thls.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/wrpll/thls.py b/artiq/gateware/drtio/wrpll/thls.py index 4216fb9fc..279c56293 100644 --- a/artiq/gateware/drtio/wrpll/thls.py +++ b/artiq/gateware/drtio/wrpll/thls.py @@ -552,7 +552,8 @@ class ProcessorImpl(Module): if pd.multiplier_shifts: if len(pd.multiplier_shifts) != 1: raise NotImplementedError - multiplier = OpUnit(lambda a, b: a * b >> pd.multiplier_shifts[0], + # work around Migen's mishandling of Verilog's cretinous operator width rules + multiplier = OpUnit(lambda a, b: Cat(a, C(0, pd.data_width)) * Cat(b, C(0, pd.data_width)) >> pd.multiplier_shifts[0], pd.data_width, pd.multiplier_stages) else: multiplier = NopUnit(pd.data_width)