forked from M-Labs/artiq
kasli: adapt to TSC and DRTIOSatellite changes
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4e4398afa6
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3d531cc923
@ -21,7 +21,7 @@ from artiq.gateware import eem
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite, SyncRTIO
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from artiq.build_soc import *
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@ -120,9 +120,10 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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self.submodules.rtio_crg = _RTIOCRG(self.platform)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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@ -138,7 +139,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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@ -662,6 +663,8 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.comb += [sfp_ctl.led.eq(channel.rx_ready)
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for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtio_memory_group = []
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self.drtio_cri = []
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@ -672,7 +675,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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drtio_memory_group.append(memory_name)
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core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
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DRTIOMaster(self.drtio_transceiver.channels[i]))
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DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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@ -704,10 +707,10 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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@ -717,7 +720,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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[self.rtio_core.cri] + self.drtio_cri)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.cri_con.switch.slave,
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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@ -799,6 +802,21 @@ class _SatelliteBase(BaseSoC):
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~self.drtio_transceiver.stable_clkin.storage)
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self.comb += sfp_ctl.led.eq(self.drtio_transceiver.channels[0].rx_ready)
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self.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0],
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self.rx_synchronizer))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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@ -829,18 +847,11 @@ class _SatelliteBase(BaseSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.drtio_transceiver.channels[0], rtio_channels,
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self.rx_synchronizer))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.submodules.drtio0_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += [
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self.drtio0.cri.connect(self.drtio0_io.cri),
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self.drtio0.async_errors.eq(self.drtio0_io.async_errors),
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]
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class Master(_MasterBase):
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