forked from M-Labs/artiq
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@ -6,7 +6,6 @@ from artiq.gateware.rtio.sed import layouts
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__all__ = ["TSCGate"]
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class TSCGate(Module):
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def __init__(self, lane_count, seqn_width, layout_fifo_payload, layout_output_network_payload):
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self.input = [Record(layouts.fifo_egress(seqn_width, layout_fifo_payload))
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