forked from M-Labs/artiq
add basic output-only untested RTIO core
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3c47f75726
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3b4bb41a19
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@ -0,0 +1,62 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.cdc import MultiReg
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class RTIOChannelO(Module):
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def __init__(self, signal, counter_width, fifo_depth):
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self.submodules.fifo = SyncFIFOBuffered([
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("timestamp", counter_width), ("level", 1)],
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fifo_depth)
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self.event = self.fifo.din
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self.writable = self.fifo.writable
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self.we = self.fifo.we
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self.underflow = Signal()
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###
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counter = Signal(counter_width)
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self.sync += counter.eq(counter + 1)
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self.sync += If(self.we & self.writable,
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If(self.event.timestamp < counter + 2,
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self.underflow.eq(1)
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)
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)
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time_hit = Signal()
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self.comb += [
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time_hit.eq(self.fifo.readable &
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(self.fifo.dout.timestamp == counter)),
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self.fifo.re.eq(time_hit)
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]
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self.sync += If(time_hit, signal.eq(self.fifo.dout.level))
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class RTIO(Module, AutoCSR):
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def __init__(self, channels, counter_width=32, ofifo_depth=8, ififo_depth=8):
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self._r_reset = CSRStorage(reset=1)
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self._r_chan_sel = CSRStorage(bits_for(len(channels)-1))
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self._r_o_timestamp = CSRStorage(counter_width)
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self._r_o_level = CSRStorage()
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self._r_o_writable = CSRStatus()
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self._r_o_we = CSR()
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self._r_o_underflow = CSRStatus()
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channel_os = []
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for n, channel in enumerate(channels):
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channel_o = InsertReset(RTIOChannelO(channel, counter_width, ofifo_depth))
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self.submodules += channel_o
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channel_os.append(channel_o)
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self.comb += [
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channel_o.reset.eq(self._r_reset.storage),
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channel_o.event.timestamp.eq(self._r_o_timestamp.storage),
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channel_o.event.level.eq(self._r_o_level.storage),
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channel_o.we.eq(self._r_o_we.re & (self._r_chan_sel == n))
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]
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channel_o = Array(channel_os)[self._r_chan_sel.storage]
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self.comb += [
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self._r_o_writable.status.eq(channel_o.writable),
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self._r_o_underflow.status.eq(channel_o.underflow)
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]
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@ -1,11 +1,14 @@
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from fractions import Fraction
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from fractions import Fraction
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from migen.fhdl.std import *
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from migen.fhdl.std import *
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from mibuild.generic_platform import *
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from misoclib import lasmicon, spiflash, gpio
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from misoclib import lasmicon, spiflash, gpio
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from misoclib.sdramphy import gensdrphy
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from misoclib.sdramphy import gensdrphy
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from misoclib.gensoc import SDRAMSoC
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from misoclib.gensoc import SDRAMSoC
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from artiqlib import rtio
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class _CRG(Module):
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class _CRG(Module):
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def __init__(self, platform, clk_freq):
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def __init__(self, platform, clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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@ -57,13 +60,21 @@ class _CRG(Module):
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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o_Q=platform.request("sdram_clock"))
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o_Q=platform.request("sdram_clock"))
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_ttl_io = [("ttl", i, Pins("C:"+str(i)), IOStandard("LVTTL")) for i in range(16)]
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class ARTIQSoC(SDRAMSoC):
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class ARTIQSoC(SDRAMSoC):
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default_platform = "papilio_pro"
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default_platform = "papilio_pro"
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csr_map = {
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"rtio": 10
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}
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csr_map.update(SDRAMSoC.csr_map)
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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clk_freq = 80*1000*1000
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clk_freq = 80*1000*1000
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SDRAMSoC.__init__(self, platform, clk_freq,
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SDRAMSoC.__init__(self, platform, clk_freq,
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cpu_reset_address=0x160000, cpu_type=cpu_type, **kwargs)
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cpu_reset_address=0x160000, cpu_type=cpu_type, **kwargs)
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platform.add_extension(_ttl_io)
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self.submodules.crg = _CRG(platform, clk_freq)
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self.submodules.crg = _CRG(platform, clk_freq)
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@ -93,5 +104,6 @@ class ARTIQSoC(SDRAMSoC):
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self.register_rom(self.spiflash.bus)
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self.register_rom(self.spiflash.bus)
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
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self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(16)])
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default_subtarget = ARTIQSoC
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default_subtarget = ARTIQSoC
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