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ad53xx: port monitor, moninj dashboard, kc705 target

This commit is contained in:
Robert Jördens 2018-03-24 16:04:02 +01:00
parent a8f0ee1c86
commit 3a0dfb7fdc
3 changed files with 10 additions and 8 deletions
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4
artiq/dashboard/moninj.py
View File

@ -224,8 +224,8 @@ def setup_from_ddb(ddb):
channel = v["arguments"]["channel"] channel = v["arguments"]["channel"]
widget = _WidgetDesc(k, comment, _DDSWidget, (bus_channel, channel, k)) widget = _WidgetDesc(k, comment, _DDSWidget, (bus_channel, channel, k))
description.add(widget) description.add(widget)
elif (v["module"] == "artiq.coredevice.ad5360" elif (v["module"] == "artiq.coredevice.ad53xx"
and v["class"] == "AD5360"): and v["class"] == "AD53XX"):
spi_device = v["arguments"]["spi_device"] spi_device = v["arguments"]["spi_device"]
spi_device = ddb[spi_device] spi_device = ddb[spi_device]
while isinstance(spi_device, str): while isinstance(spi_device, str):

10
artiq/gateware/rtio/phy/ad5360_monitor.py → artiq/gateware/rtio/phy/ad53xx_monitor.py
View File

@ -1,10 +1,10 @@
from migen import * from migen import *
from artiq.coredevice.spi2 import SPI_CONFIG_ADDR, SPI_DATA_ADDR from artiq.coredevice.spi2 import SPI_CONFIG_ADDR, SPI_DATA_ADDR
from artiq.coredevice.ad5360 import _AD5360_CMD_DATA, _AD5360_WRITE_CHANNEL from artiq.coredevice.ad53xx import AD53XX_CMD_DATA, ad53xx_cmd_write_ch
class AD5360Monitor(Module): class AD53XXMonitor(Module):
def __init__(self, spi_rtlink, ldac_rtlink=None, cs_no=0, cs_onehot=False, nchannels=32): def __init__(self, spi_rtlink, ldac_rtlink=None, cs_no=0, cs_onehot=False, nchannels=32):
self.probes = [Signal(16) for i in range(nchannels)] self.probes = [Signal(16) for i in range(nchannels)]
@ -39,8 +39,10 @@ class AD5360Monitor(Module):
) )
] ]
writes = {(_AD5360_CMD_DATA | _AD5360_WRITE_CHANNEL(i)) >> 16: t.eq(spi_oif.data[8:24]) writes = {
for i, t in enumerate(write_targets)} ad53xx_cmd_write_ch(channel=i, value=0, op=AD53XX_CMD_DATA) >> 16:
t.eq(spi_oif.data[8:24])
for i, t in enumerate(write_targets)}
self.sync.rio_phy += [ self.sync.rio_phy += [
If(spi_oif.stb & (spi_oif.address == SPI_DATA_ADDR), If(spi_oif.stb & (spi_oif.address == SPI_DATA_ADDR),
Case(spi_oif.data[24:], writes) Case(spi_oif.data[24:], writes)

4
artiq/gateware/targets/kc705.py
View File

@ -17,7 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
from artiq.gateware.amp import AMPSoC from artiq.gateware.amp import AMPSoC
from artiq.gateware import rtio, nist_clock, nist_qc2 from artiq.gateware import rtio, nist_clock, nist_qc2
from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series, from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
dds, spi2, ad5360_monitor) dds, spi2, ad53xx_monitor)
from artiq.build_soc import build_artiq_soc from artiq.build_soc import build_artiq_soc
from artiq import __version__ as artiq_version from artiq import __version__ as artiq_version
@ -351,7 +351,7 @@ class NIST_CLOCK(_StandaloneBase):
self.submodules += ldac_phy self.submodules += ldac_phy
rtio_channels.append(rtio.Channel.from_phy(ldac_phy)) rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
dac_monitor = ad5360_monitor.AD5360Monitor(sdac_phy.rtlink, ldac_phy.rtlink) dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink, ldac_phy.rtlink)
self.submodules += dac_monitor self.submodules += dac_monitor
sdac_phy.probes.extend(dac_monitor.probes) sdac_phy.probes.extend(dac_monitor.probes)