forked from M-Labs/artiq
rtio: fix DMA TimeOffset stream.connect
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d4cb1eb998
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3931d8097b
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@ -194,7 +194,7 @@ class TimeOffset(Module, AutoCSR):
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pipe_ce = Signal()
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pipe_ce = Signal()
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self.sync += \
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self.sync += \
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If(pipe_ce,
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If(pipe_ce,
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self.source.payload.connect(self.sink.payload,
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self.sink.payload.connect(self.source.payload,
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leave_out={"timestamp"}),
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leave_out={"timestamp"}),
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self.source.payload.timestamp.eq(self.sink.payload.timestamp
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self.source.payload.timestamp.eq(self.sink.payload.timestamp
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+ self.time_offset.storage),
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+ self.time_offset.storage),
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