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ad9910/2: add sw invariant only when passed

This commit is contained in:
Robert Jördens 2018-03-07 19:00:50 +00:00 committed by Robert Jordens
parent 82831a85b6
commit 37ec97eb28
2 changed files with 4 additions and 2 deletions
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3
artiq/coredevice/ad9910.py
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@ -49,7 +49,7 @@ class AD9910:
:param pll_cp: DDS PLL charge pump setting. :param pll_cp: DDS PLL charge pump setting.
:param pll_vco: DDS PLL VCO range selection. :param pll_vco: DDS PLL VCO range selection.
""" """
kernel_invariants = {"chip_select", "cpld", "core", "bus", "sw", kernel_invariants = {"chip_select", "cpld", "core", "bus",
"ftw_per_hz", "pll_n", "pll_cp", "pll_vco"} "ftw_per_hz", "pll_n", "pll_cp", "pll_vco"}
def __init__(self, dmgr, chip_select, cpld_device, sw_device=None, def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
@ -61,6 +61,7 @@ class AD9910:
self.chip_select = chip_select self.chip_select = chip_select
if sw_device: if sw_device:
self.sw = dmgr.get(sw_device) self.sw = dmgr.get(sw_device)
self.kernel_invariants.add("sw")
assert 12 <= pll_n <= 127 assert 12 <= pll_n <= 127
self.pll_n = pll_n self.pll_n = pll_n
assert self.cpld.refclk/4 <= 60e6 assert self.cpld.refclk/4 <= 60e6

3
artiq/coredevice/ad9912.py
View File

@ -24,7 +24,7 @@ class AD9912:
f_ref*pll_n where f_ref is the reference frequency (set in the parent f_ref*pll_n where f_ref is the reference frequency (set in the parent
Urukul CPLD instance). Urukul CPLD instance).
""" """
kernel_invariants = {"chip_select", "cpld", "core", "bus", "sw", kernel_invariants = {"chip_select", "cpld", "core", "bus",
"ftw_per_hz", "sysclk", "pll_n"} "ftw_per_hz", "sysclk", "pll_n"}
def __init__(self, dmgr, chip_select, cpld_device, sw_device=None, def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
@ -36,6 +36,7 @@ class AD9912:
self.chip_select = chip_select self.chip_select = chip_select
if sw_device: if sw_device:
self.sw = dmgr.get(sw_device) self.sw = dmgr.get(sw_device)
self.kernel_invariants.add("sw")
self.pll_n = pll_n self.pll_n = pll_n
self.sysclk = self.cpld.refclk*pll_n self.sysclk = self.cpld.refclk*pll_n
assert self.sysclk <= 1e9 assert self.sysclk <= 1e9