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rtio/ttl: expose OE

This commit is contained in:
Sebastien Bourdeauducq 2019-10-16 18:48:20 +08:00
parent bc060b7f01
commit 37d0a5dc19
2 changed files with 12 additions and 4 deletions
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8
artiq/gateware/rtio/phy/ttl_serdes_generic.py
View File

@ -67,6 +67,8 @@ class InOut(Module):
override_oe = Signal() override_oe = Signal()
self.overrides = [override_en, override_o, override_oe] self.overrides = [override_en, override_o, override_oe]
# Output enable, for interfacing to external buffers.
self.oe = Signal()
# LSB of the input state (for edge detection; arbitrary choice, support for # LSB of the input state (for edge detection; arbitrary choice, support for
# short pulses will need a more involved solution). # short pulses will need a more involved solution).
self.input_state = Signal() self.input_state = Signal()
@ -82,15 +84,17 @@ class InOut(Module):
override_en=override_en, override_o=override_o) override_en=override_en, override_o=override_o)
oe_k = Signal() oe_k = Signal()
self.oe.attr.add("no_retiming")
self.sync.rio_phy += [ self.sync.rio_phy += [
If(self.rtlink.o.stb & (self.rtlink.o.address == 1), If(self.rtlink.o.stb & (self.rtlink.o.address == 1),
oe_k.eq(self.rtlink.o.data[0])), oe_k.eq(self.rtlink.o.data[0])),
If(override_en, If(override_en,
serdes.oe.eq(override_oe) self.oe.eq(override_oe)
).Else( ).Else(
serdes.oe.eq(oe_k) self.oe.eq(oe_k)
) )
] ]
self.comb += serdes.oe.eq(self.oe)
# Input # Input
sensitivity = Signal(2) sensitivity = Signal(2)

8
artiq/gateware/rtio/phy/ttl_simple.py
View File

@ -90,6 +90,8 @@ class InOut(Module):
self.overrides = [override_en, override_o, override_oe] self.overrides = [override_en, override_o, override_oe]
self.probes = [] self.probes = []
# Output enable, for interfacing to external buffers.
self.oe = Signal()
# Registered copy of the input state, in the rio_phy clock domain. # Registered copy of the input state, in the rio_phy clock domain.
self.input_state = Signal() self.input_state = Signal()
@ -101,6 +103,7 @@ class InOut(Module):
o_k = Signal() o_k = Signal()
oe_k = Signal() oe_k = Signal()
self.oe.attr.add("no_retiming")
self.sync.rio_phy += [ self.sync.rio_phy += [
If(self.rtlink.o.stb, If(self.rtlink.o.stb,
If(self.rtlink.o.address == 0, o_k.eq(self.rtlink.o.data[0])), If(self.rtlink.o.address == 0, o_k.eq(self.rtlink.o.data[0])),
@ -108,12 +111,13 @@ class InOut(Module):
), ),
If(override_en, If(override_en,
ts.o.eq(override_o), ts.o.eq(override_o),
ts.oe.eq(override_oe) self.oe.eq(override_oe)
).Else( ).Else(
ts.o.eq(o_k), ts.o.eq(o_k),
ts.oe.eq(oe_k) self.oe.eq(oe_k)
) )
] ]
self.comb += ts.oe.eq(self.oe)
sample = Signal() sample = Signal()
self.sync.rio += [ self.sync.rio += [
sample.eq(0), sample.eq(0),