forked from M-Labs/artiq
suservo: refactor, constrain
* remove DiffMixin, move pad layout handling to pads * add input delay constraints, IDELAYs
This commit is contained in:
parent
d0258b9b2d
commit
37c186a0fc
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@ -5,8 +5,6 @@ from collections import namedtuple
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from migen import *
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from migen.genlib import io
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from .tools import DiffMixin
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logger = logging.getLogger(__name__)
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@ -28,7 +26,7 @@ ADCParams = namedtuple("ADCParams", [
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])
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class ADC(Module, DiffMixin):
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class ADC(Module):
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"""Multi-lane, multi-channel, triggered, source-synchronous, serial
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ADC interface.
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@ -49,7 +47,7 @@ class ADC(Module, DiffMixin):
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# collect sdo lines
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sdo = []
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for i in string.ascii_lowercase[:p.lanes]:
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sdo.append(self._diff(pads, "sdo" + i))
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sdo.append(getattr(pads, "sdo" + i))
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assert p.lanes == len(sdo)
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# set up counters for the four states CNVH, CONV, READ, RTT
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@ -71,13 +69,6 @@ class ADC(Module, DiffMixin):
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)
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]
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sck_en = Signal()
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if hasattr(pads, "sck_en"):
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self.sync += pads.sck_en.eq(sck_en) # ODDR delay
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self.specials += io.DDROutput(0, sck_en,
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self._diff(pads, "sck", output=True))
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cnv_b = Signal()
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self.comb += self._diff(pads, "cnv_b", output=True).eq(cnv_b)
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self.submodules.fsm = fsm = FSM("IDLE")
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fsm.act("IDLE",
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self.done.eq(1),
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@ -88,7 +79,7 @@ class ADC(Module, DiffMixin):
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)
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fsm.act("CNVH",
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count_load.eq(p.t_conv - 2), # account for sck ODDR delay
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cnv_b.eq(1),
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pads.cnv.eq(1),
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If(count_done,
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NextState("CONV")
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)
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@ -102,7 +93,7 @@ class ADC(Module, DiffMixin):
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fsm.act("READ",
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self.reading.eq(1),
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count_load.eq(p.t_rtt), # account for sck ODDR delay
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sck_en.eq(1),
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pads.sck_en.eq(1),
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If(count_done,
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NextState("RTT")
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)
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@ -118,22 +109,25 @@ class ADC(Module, DiffMixin):
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sck_en_ret = pads.sck_en_ret
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except AttributeError:
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sck_en_ret = 1
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self.clkout_io = Signal()
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self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
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self.comb += [
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# falling clkout makes two bits available
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self.cd_ret.clk.eq(~pads.clkout)
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]
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k = p.channels//p.lanes
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assert 2*t_read == k*p.width
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for i, sdo in enumerate(sdo):
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sdo_sr0 = Signal(t_read - 1)
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sdo_sr1 = Signal(t_read - 1)
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sdo_ddr = Signal(2)
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self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0],
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~self.clkout_io)
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self.sync.ret += [
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If(self.reading & sck_en_ret,
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sdo_sr0.eq(Cat(sdo_ddr[0], sdo_sr0)),
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sdo_sr1.eq(Cat(sdo_ddr[1], sdo_sr1))
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sdo_sr0.eq(Cat(sdo[0], sdo_sr0)),
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sdo_sr1.eq(Cat(sdo[1], sdo_sr1))
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)
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]
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self.comb += [
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Cat(reversed([self.data[i*k + j] for j in range(k)])).eq(
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Cat(sdo_ddr, zip(sdo_sr0, sdo_sr1)))
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Cat(sdo, zip(sdo_sr0, sdo_sr1)))
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]
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@ -36,7 +36,7 @@ class DDS(spi.SPISimple):
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)
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]
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io_update = self._diff(pads, "io_update", output=True)
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io_update = pads.io_update
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# this assumes that the cycle time (1/125 MHz = 8 ns) is >1 SYNC_CLK
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# cycle (1/250 MHz = 4ns)
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done = Signal()
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@ -1,24 +1,77 @@
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from migen import *
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from migen.genlib.io import DifferentialOutput
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from migen.genlib.io import DifferentialOutput, DifferentialInput, DDROutput
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class SamplerPads(Module):
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def __init__(self, platform, eem0, eem1):
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self.sck_p, self.sck_n = [
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platform.request("{}_adc_spi_{}".format(eem0, pol), 0).clk
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for pol in "pn"]
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pads = platform.request("{}_cnv".format(eem0), 0)
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self.cnv_b_p, self.cnv_b_n = pads.p, pads.n
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pads = platform.request("{}_sdr".format(eem0), 0)
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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dp, dn = [
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platform.request("{}_adc_data_{}".format(eem0, pol), 0)
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for pol in "pn"]
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self.clkout_p, self.clkout_n = dp.clkout, dn.clkout
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self.sdoa_p, self.sdoa_n = dp.sdoa, dn.sdoa
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self.sdob_p, self.sdob_n = dp.sdob, dn.sdob
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self.sdoc_p, self.sdoc_n = dp.sdoc, dn.sdoc
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self.sdod_p, self.sdod_n = dp.sdod, dn.sdod
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self.sck_en = Signal()
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self.cnv = Signal()
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self.clkout = Signal()
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spip = platform.request("{}_adc_spi_p".format(eem0))
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spin = platform.request("{}_adc_spi_n".format(eem0))
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cnv = platform.request("{}_cnv".format(eem0))
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sdr = platform.request("{}_sdr".format(eem0))
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dp = platform.request("{}_adc_data_p".format(eem0))
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dn = platform.request("{}_adc_data_n".format(eem0))
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clkout_se = Signal()
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clkout_d = Signal()
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sck = Signal()
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self.specials += [
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DifferentialOutput(self.cnv, cnv.p, cnv.n),
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DifferentialOutput(1, sdr.p, sdr.n),
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DDROutput(0, self.sck_en, sck),
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DifferentialOutput(sck, spip.clk, spin.clk),
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DifferentialInput(dp.clkout, dn.clkout, clkout_se),
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Instance(
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"IDELAYE2",
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p_HIGH_PERFORMANCE_MODE="TRUE", p_IDELAY_TYPE="FIXED",
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p_SIGNAL_PATTERN="CLOCK", p_IDELAY_VALUE=0,
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p_REFCLK_FREQUENCY=200.,
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i_IDATAIN=clkout_se, o_DATAOUT=clkout_d),
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Instance("BUFR", i_I=clkout_d, o_O=self.clkout)
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]
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# here to be early before the input delays below to have the clock
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# available
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self.clkout_p = dp.clkout # availabel for false paths
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platform.add_platform_command(
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"create_clock -name {clk} -period 8 [get_nets {clk}]",
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clk=dp.clkout)
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# platform.add_period_constraint(sampler_pads.clkout_p, 8.)
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for i in "abcd":
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sdo_se = Signal()
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sdo_d = Signal()
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sdo = Signal(2)
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setattr(self, "sdo{}".format(i), sdo)
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sdop = getattr(dp, "sdo{}".format(i))
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sdon = getattr(dn, "sdo{}".format(i))
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self.specials += [
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DifferentialInput(sdop, sdon, sdo_se),
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Instance(
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"IDELAYE2",
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p_HIGH_PERFORMANCE_MODE="TRUE", p_IDELAY_TYPE="FIXED",
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p_SIGNAL_PATTERN="DATA", p_IDELAY_VALUE=31,
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p_REFCLK_FREQUENCY=200.,
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i_IDATAIN=sdo_se, o_DATAOUT=sdo_d),
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Instance("IDDR",
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p_DDR_CLK_EDGE="SAME_EDGE",
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i_C=~self.clkout, i_CE=1, i_S=0, i_R=0,
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i_D=sdo_d, o_Q1=sdo[0], o_Q2=sdo[1]) # sdo[1] older
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]
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# 4, -0+1.5 hold (t_HSDO_DDR), -0.2+0.2 skew
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platform.add_platform_command(
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"set_input_delay -clock {clk} "
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"-max 1.6 [get_ports {port}]\n"
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"set_input_delay -clock {clk} "
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"-min -0.1 [get_ports {port}]\n"
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"set_input_delay -clock {clk} "
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"-max 1.6 [get_ports {port}] -clock_fall -add_delay\n"
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"set_input_delay -clock {clk} "
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"-min -0.1 [get_ports {port}] -clock_fall -add_delay",
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clk=dp.clkout, port=sdop)
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class UrukulPads(Module):
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@ -37,7 +90,10 @@ class UrukulPads(Module):
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DifferentialOutput(self.io_update, ioup[i].p, ioup[i].n))
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for i in range(2)]
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for i in range(8):
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setattr(self, "mosi{}_p".format(i),
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getattr(spip[i // 4], "mosi{}".format(i % 4)))
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setattr(self, "mosi{}_n".format(i),
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mosi = Signal()
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setattr(self, "mosi{}".format(i), mosi)
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self.specials += [
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DifferentialOutput(mosi,
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getattr(spip[i // 4], "mosi{}".format(i % 4)),
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getattr(spin[i // 4], "mosi{}".format(i % 4)))
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]
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@ -5,8 +5,6 @@ from migen import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib import io
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from .tools import DiffMixin
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logger = logging.getLogger(__name__)
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@ -19,7 +17,7 @@ SPIParams = namedtuple("SPIParams", [
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])
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class SPISimple(Module, DiffMixin):
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class SPISimple(Module):
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"""Simple reduced SPI interface.
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* Multiple MOSI lines
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@ -39,9 +37,8 @@ class SPISimple(Module, DiffMixin):
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assert p.clk >= 1
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cs_n = self._diff(pads, "cs_n", output=True)
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clk = self._diff(pads, "clk", output=True)
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cs_n = pads.cs_n
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clk = pads.clk
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cnt = Signal(max=max(2, p.clk), reset_less=True)
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cnt_done = Signal()
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cnt_next = Signal()
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@ -58,7 +55,7 @@ class SPISimple(Module, DiffMixin):
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for i, d in enumerate(self.data):
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self.comb += [
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self._diff(pads, "mosi{}".format(i), output=True).eq(d[-1])
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getattr(pads, "mosi{}".format(i)).eq(d[-1])
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]
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bits = Signal(max=p.width + 1, reset_less=True)
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@ -1,19 +0,0 @@
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from migen import *
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from migen.genlib import io
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class DiffMixin:
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def _diff(self, pads, name, output=False):
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"""Retrieve the single-ended ``Signal()`` ``name`` from
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``pads`` and in its absence retrieve the differential signal with the
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pin pairs ``name_p`` and ``name_n``. Do so as an output if ``output``,
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otherwise make a differential input."""
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if hasattr(pads, name):
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return getattr(pads, name)
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sig = Signal()
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p, n = (getattr(pads, name + "_" + s) for s in "pn")
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if output:
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self.specials += io.DifferentialOutput(sig, p, n)
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else:
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self.specials += io.DifferentialInput(p, n, sig)
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return sig
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@ -540,20 +540,6 @@ class SUServo(_StandaloneBase):
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su = ClockDomainsRenamer({"sys": "rio_phy"})(su)
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self.submodules += sampler_pads, urukul_pads, su
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self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
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clkout = Signal()
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clkout_fabric = Signal()
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self.specials += [
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DifferentialInput(
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sampler_pads.clkout_p, sampler_pads.clkout_n, clkout),
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Instance("BUFH", i_I=clkout, o_O=clkout_fabric),
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Instance("BUFIO", i_I=clkout, o_O=su.adc.clkout_io)
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]
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self.comb += [
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# falling clkout makes two bits available
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self.cd_ret.clk.eq(~clkout_fabric)
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]
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ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
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self.submodules += ctrls
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rtio_channels.extend(rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
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@ -603,29 +589,12 @@ class SUServo(_StandaloneBase):
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self.add_rtio(rtio_channels)
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platform.add_period_constraint(sampler_pads.clkout_p, 8.)
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platform.add_false_path_constraints(
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sampler_pads.clkout_p,
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self.rtio_crg.cd_rtio.clk)
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platform.add_false_path_constraints(
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sampler_pads.clkout_p,
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self.crg.cd_sys.clk)
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for i in "abcd":
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port = getattr(sampler_pads, "sdo{}_p".format(i))
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platform.add_platform_command(
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-max 6 [get_ports {port}]\n"
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-min 3.5 [get_ports {port}]\n"
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-max 6 [get_ports {port}] -clock_fall -add_delay\n"
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"set_input_delay -clock [get_clocks "
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"-include_generated_clocks -of [get_nets {clk}]] "
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"-min 3.5 [get_ports {port}] -clock_fall -add_delay",
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clk=sampler_pads.clkout_p, port=port)
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class SYSU(_StandaloneBase):
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@ -8,57 +8,6 @@ from migen.genlib import io
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from artiq.gateware.suservo.adc_ser import ADC, ADCParams
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class DDROutputImpl(Module):
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def __init__(self, i1, i2, o, clk):
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do_clk0 = Signal(reset_less=True)
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do_j1 = Signal(reset_less=True)
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do_j2 = Signal(reset_less=True)
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do_j3 = Signal(reset_less=True)
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self.sync.async += [
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do_clk0.eq(clk),
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do_j1.eq(i1),
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do_j2.eq(i2),
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If(Cat(do_clk0, clk) == 0b10,
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o.eq(do_j1),
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do_j3.eq(do_j2),
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).Elif(Cat(do_clk0, clk) == 0b01,
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o.eq(do_j3),
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)
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]
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class DDROutput:
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@staticmethod
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def lower(dr):
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return DDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
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class DDRInputImpl(Module):
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def __init__(self, i, o1, o2, clk):
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di_clk0 = Signal(reset_less=True)
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# SAME_EDGE_PIPELINED is effectively one register for o1
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# (during rising clock)
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di_j1 = Signal(reset_less=True)
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di_j2 = Signal(reset_less=True)
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di_j3 = Signal(reset_less=True)
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self.sync.async += [
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di_clk0.eq(clk),
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di_j1.eq(i),
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If(Cat(di_clk0, clk) == 0b10,
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di_j3.eq(di_j1),
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o1.eq(di_j3),
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o2.eq(di_j2)
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).Elif(Cat(di_clk0, clk) == 0b01,
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di_j2.eq(di_j1)
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)
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]
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class DDRInput:
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@staticmethod
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def lower(dr):
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return DDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk)
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class TB(Module):
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def __init__(self, params):
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@ -66,7 +15,7 @@ class TB(Module):
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self.sck = Signal()
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self.clkout = Signal(reset_less=True)
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self.cnv_b = Signal()
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self.cnv = Signal()
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self.sck_en = Signal()
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self.sck_en_ret = Signal()
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@ -75,12 +24,6 @@ class TB(Module):
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cd_adc = ClockDomain("adc", reset_less=True)
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self.clock_domains += cd_adc
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self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
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self.comb += [
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# falling clkout makes two bits available
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self.cd_ret.clk.eq(~self.clkout)
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]
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self.sdo = []
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self.data = [Signal((p.width, True), reset_less=True)
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for i in range(p.channels)]
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@ -88,23 +31,21 @@ class TB(Module):
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srs = []
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for i in range(p.lanes):
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name = "sdo" + string.ascii_lowercase[i]
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sdo = Signal(name=name, reset_less=True)
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sdo = Signal(2, name=name, reset_less=True)
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self.sdo.append(sdo)
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setattr(self, name, sdo)
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sr = Signal(p.width*p.channels//p.lanes, reset_less=True)
|
||||
srs.append(sr)
|
||||
self.specials += io.DDROutput(
|
||||
# one for async
|
||||
self._dly(sr[-1], -1), self._dly(sr[-2], -1), sdo)
|
||||
self.sync.adc += [
|
||||
sdo.eq(Cat(self._dly(sr[-1], 3), self._dly(sr[-2], 3))),
|
||||
If(adc_sck_en,
|
||||
sr[2:].eq(sr)
|
||||
)
|
||||
]
|
||||
cnv_b_old = Signal(reset_less=True)
|
||||
cnv_old = Signal(reset_less=True)
|
||||
self.sync.async += [
|
||||
cnv_b_old.eq(self.cnv_b),
|
||||
If(Cat(cnv_b_old, self.cnv_b) == 0b10,
|
||||
cnv_old.eq(self.cnv),
|
||||
If(Cat(cnv_old, self.cnv) == 0b10,
|
||||
sr.eq(Cat(reversed(self.data[2*i:2*i + 2]))),
|
||||
)
|
||||
]
|
||||
|
@ -130,7 +71,6 @@ def main():
|
|||
tb = TB(params)
|
||||
adc = ADC(tb, params)
|
||||
tb.submodules += adc
|
||||
tb.comb += adc.clkout_io.eq(tb.clkout)
|
||||
|
||||
def run(tb):
|
||||
dut = adc
|
||||
|
@ -156,10 +96,7 @@ def main():
|
|||
"ret": (8, 0),
|
||||
"async": (2, 0),
|
||||
},
|
||||
special_overrides={
|
||||
io.DDROutput: DDROutput,
|
||||
io.DDRInput: DDRInput
|
||||
})
|
||||
)
|
||||
|
||||
|
||||
class ADCTest(unittest.TestCase):
|
||||
|
|
|
@ -23,7 +23,6 @@ class ServoSim(servo.Servo):
|
|||
|
||||
servo.Servo.__init__(self, self.adc_tb, self.dds_tb,
|
||||
adc_p, iir_p, dds_p)
|
||||
self.adc_tb.comb += self.adc.clkout_io.eq(self.adc_tb.clkout)
|
||||
|
||||
def test(self):
|
||||
assert (yield self.done)
|
||||
|
|
Loading…
Reference in New Issue