forked from M-Labs/artiq
artiq_flash: fix Metlino support
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88b6496c8c
commit
34c61db790
@ -223,7 +223,7 @@ class ProgrammerXC7(Programmer):
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"xc7_program xc7.tap")
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class ProgrammerSaymaMetlino(Programmer):
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class ProgrammerSayma(Programmer):
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_sector_size = 0x10000
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def __init__(self, client, preinit_script):
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@ -260,6 +260,39 @@ class ProgrammerSaymaMetlino(Programmer):
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add_commands(self._script, "xcu_program xcu.tap")
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class ProgrammerMetlino(Programmer):
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_sector_size = 0x10000
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def __init__(self, client, preinit_script):
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Programmer.__init__(self, client, preinit_script)
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add_commands(self._board_script,
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"source {}".format(self._transfer_script("fpga/xilinx-xadc.cfg")),
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"interface ftdi",
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"ftdi_device_desc \"Quad RS232-HS\"",
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"ftdi_vid_pid 0x0403 0x6011",
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"ftdi_channel 0",
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# EN_USB_JTAG on ADBUS7: out, high
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# nTRST on ADBUS4: out, high, but R46 is DNP
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"ftdi_layout_init 0x0098 0x008b",
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"reset_config none",
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"adapter_khz 5000",
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"transport select jtag",
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"set CHIP XCKU040",
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"source {}".format(self._transfer_script("cpld/xilinx-xcu.cfg")))
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self.add_flash_bank("spi0", "xcu", index=0)
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self.add_flash_bank("spi1", "xcu", index=1)
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add_commands(self._script, "echo \"AMC FPGA XADC:\"", "xadc_report xcu.tap")
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def load_proxy(self):
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self.load(find_proxy_bitfile("bscan_spi_xcku040-sayma.bit"), pld=0)
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def start(self):
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add_commands(self._script, "xcu_program xcu.tap")
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def main():
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args = get_argparser().parse_args()
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init_logger(args)
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@ -273,7 +306,7 @@ def main():
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"firmware": ("spi0", 0x450000),
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},
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"sayma": {
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"programmer": ProgrammerSaymaMetlino,
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"programmer": ProgrammerSayma,
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi1", 0x000000),
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"storage": ("spi1", 0x040000),
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@ -281,7 +314,7 @@ def main():
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"rtm_gateware": ("spi1", 0x200000),
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},
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"metlino": {
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"programmer": ProgrammerSaymaMetlino,
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"programmer": ProgrammerMetlino,
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi1", 0x000000),
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"storage": ("spi1", 0x040000),
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