forked from M-Labs/artiq
firmware: si5324 cleanups/fixes
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@ -23,14 +23,14 @@ fn pca9548_select(channel: u8) -> Result<()> {
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// NOTE: the logical parameters DO NOT MAP to physical values written
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// into registers. They have to be mapped; see the datasheet.
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// DSPLLsim reports the logical parameters in the design summary, not
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// the physical register values (but those are present separately).
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// the physical register values.
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pub struct FrequencySettings {
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n1_hs: u8,
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nc1_ls: u32,
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n2_hs: u8,
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n2_ls: u32,
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n31: u32,
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n32: u32
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pub n1_hs: u8,
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pub nc1_ls: u32,
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pub n2_hs: u8,
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pub n2_ls: u32,
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pub n31: u32,
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pub n32: u32
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}
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fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySettings> {
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@ -62,7 +62,7 @@ fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySetti
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("n1_hs has an invalid value")
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_ => return Err("N1_HS has an invalid value")
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},
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nc1_ls: settings.nc1_ls - 1,
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n2_hs: match settings.n2_hs {
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@ -74,7 +74,7 @@ fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySetti
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9 => 0b101,
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10 => 0b110,
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11 => 0b111,
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_ => return Err("n2_hs has an invalid value")
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_ => return Err("N2_HS has an invalid value")
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},
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n2_ls: settings.n2_ls - 1,
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n31: settings.n31 - 1,
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