From 346cca9e904572d9397c3f5eb56c595bbd7942c5 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 21 Oct 2014 18:40:08 +0800
Subject: [PATCH] soc/target: remap RTIO to avoid conflict with spiflash and
 ddrphy in MiSoC

---
 soc/targets/artiq.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py
index 15a45823e..aff07b227 100644
--- a/soc/targets/artiq.py
+++ b/soc/targets/artiq.py
@@ -41,7 +41,7 @@ class _TestGen(Module):
 
 class ARTIQMiniSoC(BaseSoC):
     csr_map = {
-        "rtio":            10
+        "rtio":            12
     }
     csr_map.update(BaseSoC.csr_map)