srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

phaser: bypass gtx phalign

This commit is contained in:
Robert Jördens 2016-10-14 00:59:53 +02:00
parent 89150c9817
commit 342d6d756e
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
artiq/gateware/targets/kc705.py
View File

@ -466,6 +466,7 @@ class AD9154JESD(Module, AutoCSR):
phy = JESD204BPhyTX(
qpll, platform.request("ad9154_jesd", i), fabric_freq)
platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO
platform.add_false_path_constraints(
self.cd_jesd.clk,
phy.gtx.cd_tx.clk)