From 342b9e977ee594d49cdb3c233c89bc796a391cc4 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Fri, 18 Nov 2016 15:46:59 +0100
Subject: [PATCH] phaser: cap phy data width to 64 temporarily

---
 artiq/gateware/rtio/phy/sawg.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/artiq/gateware/rtio/phy/sawg.py b/artiq/gateware/rtio/phy/sawg.py
index 84094f5a2..5b15806e6 100644
--- a/artiq/gateware/rtio/phy/sawg.py
+++ b/artiq/gateware/rtio/phy/sawg.py
@@ -16,7 +16,8 @@ class Channel(_ChannelPHY):
         _ChannelPHY.__init__(self, *args, **kwargs)
         self.phys = []
         for i in self.i:
-            rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
+            rl = rtlink.Interface(rtlink.OInterface(
+                min(64, len(i.payload))))  # FIXME
             self.comb += [
                 i.stb.eq(rl.o.stb),
                 rl.o.busy.eq(~i.ack),