forked from M-Labs/artiq
libboard: complete but undebugged support for HMC830/7043 programming
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@ -1,6 +1,151 @@
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include!(concat!(env!("OUT_DIR"), "/hmc7043_writes.rs"));
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/*
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* HMC830 config:
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* 100MHz input, 1GHz output
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* fvco = (refclk / r_divider) * n_divider
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* fout = fvco/2
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*
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* HMC7043 config:
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* dac clock: 1GHz (div=1)
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* fpga clock: 250MHz (div=4)
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* sysref clock: 15.625MHz (div=64)
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*/
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mod hmc830 {
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use csr;
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const HMC830_WRITES: [(u8, u32); 16] = [
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(0x0, 0x20),
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(0x1, 0x2),
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(0x2, 0x2), // r_divider
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(0x5, 0x1628),
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(0x5, 0x60a0),
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(0x5, 0xe110),
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(0x5, 0x2818),
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(0x5, 0x0),
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(0x6, 0x303ca),
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(0x7, 0x14d),
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(0x8, 0xc1beff),
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(0x9, 0x153fff),
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(0xa, 0x2046),
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(0xb, 0x7c061),
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(0xf, 0x81),
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(0x3, 0x28), // n_divider
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];
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fn spi_setup() {
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(0);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(0);
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csr::converter_spi::clk_div_write_write(8);
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csr::converter_spi::clk_div_read_write(8);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC830_CS);
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csr::converter_spi::offline_write(0);
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}
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}
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fn write(addr: u8, data: u32) {
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let cmd = (0 << 6) | addr;
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let val = ((cmd as u32) << 24) | data;
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unsafe {
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csr::converter_spi::xfer_len_write_write(32);
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csr::converter_spi::xfer_len_read_write(0);
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csr::converter_spi::data_write_write(val << (32-31));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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}
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}
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fn read(addr: u8) -> u32 {
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let cmd = (1 << 6) | addr;
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let val = (cmd as u32) << 24;
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unsafe {
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csr::converter_spi::xfer_len_write_write(7);
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csr::converter_spi::xfer_len_read_write(25);
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csr::converter_spi::data_write_write(val << (32-31));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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csr::converter_spi::data_read_read()
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}
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}
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pub fn init() -> Result<(), &'static str> {
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spi_setup();
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let id = read(0);
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if id != 0xa7975 {
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error!("invalid HMC830 ID: 0x{:08x}", id);
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return Err("invalid HMC830 identification");
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}
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for &(addr, data) in HMC830_WRITES.iter() {
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write(addr, data);
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}
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Ok(())
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}
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}
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mod hmc7043 {
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use csr;
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include!(concat!(env!("OUT_DIR"), "/hmc7043_writes.rs"));
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fn spi_setup() {
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(0);
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csr::converter_spi::clk_polarity_write(0);
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csr::converter_spi::clk_phase_write(0);
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csr::converter_spi::lsb_first_write(0);
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csr::converter_spi::half_duplex_write(1);
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csr::converter_spi::clk_div_write_write(8);
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csr::converter_spi::clk_div_read_write(8);
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csr::converter_spi::cs_write(1 << csr::CONFIG_CONVERTER_SPI_HMC7043_CS);
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csr::converter_spi::offline_write(0);
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}
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}
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fn write(addr: u16, data: u8) {
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let cmd = (0 << 15) | addr;
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let val = ((cmd as u32) << 8) | data as u32;
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unsafe {
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csr::converter_spi::xfer_len_write_write(24);
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csr::converter_spi::xfer_len_read_write(0);
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csr::converter_spi::data_write_write(val << (32-24));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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}
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}
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fn read(addr: u16) -> u8 {
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let cmd = (0 << 15) | addr;
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let val = (cmd as u32) << 8;
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unsafe {
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csr::converter_spi::xfer_len_write_write(16);
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csr::converter_spi::xfer_len_read_write(8);
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csr::converter_spi::data_write_write(val << (32-24));
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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csr::converter_spi::data_read_read() as u8
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}
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}
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pub fn init() -> Result<(), &'static str> {
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spi_setup();
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let id = (read(0x78) as u32) << 16 | (read(0x79) as u32) << 8 | read(0x7a) as u32;
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if id != 0xf17904 {
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error!("invalid HMC7043 ID: 0x{:08x}", id);
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return Err("invalid HMC7043 identification");
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}
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for &(addr, data) in HMC7043_WRITES.iter() {
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write(addr, data);
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}
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Ok(())
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}
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}
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pub fn init() -> Result<(), &'static str> {
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error!("HMC830/7043 support is not implemented");
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Ok(())
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hmc830::init()?;
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hmc7043::init()
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}
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