forked from M-Labs/artiq
gateware/soc: use new SDRAM API call
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@ -20,7 +20,7 @@ class AMPSoC:
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self.submodules.timer0 = timer.Timer(width=64)
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self.submodules.timer0 = timer.Timer(width=64)
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self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
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self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
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self.add_wb_sdram_if(self.kernel_cpu.wb_sdram)
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self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
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self.submodules.mailbox = amp.Mailbox()
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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