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sayma: disable SERDES TTL entirely

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Timing closure becomes very random, even at 4X.
This commit is contained in:
Sebastien Bourdeauducq 2018-03-21 13:03:46 +08:00
parent f8c2d54e75
commit 32f22f4c9c
1 changed files with 7 additions and 57 deletions
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64
artiq/gateware/targets/sayma_amc.py
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@ -31,7 +31,7 @@ from artiq.gateware.amp import AMPSoC
from artiq.gateware import serwb
from artiq.gateware import remote_csr
from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale, sawg
from artiq.gateware.rtio.phy import ttl_simple, sawg
from artiq.gateware.drtio.transceiver import gth_ultrascale
from artiq.gateware.drtio.siphaser import SiPhaser7Series
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
@ -126,54 +126,6 @@ class AD9154NoSAWG(Module, AutoCSR):
for i in range(len(conv) // len(ramp))))
# Generates a X2 clock that can be used for 4:1 SERDES ratio.
class _RTIOClockMultiplier(Module):
def __init__(self, platform, rtio_clk_freq):
self.clock_domains.cd_rtio_serdes = ClockDomain()
self.clock_domains.cd_rtiox_serdes = ClockDomain(reset_less=True)
# See "Global Clock Network Deskew Using Two BUFGs" in ug572.
# See also AR#67885.
clkfbout = Signal()
clkfbin = Signal()
rtio_clk = Signal()
rtiox_clk = Signal()
self.specials += [
Instance("MMCME2_BASE",
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
i_CLKIN1=ClockSignal("rtio"),
i_RST=ResetSignal("rtio"),
p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
p_CLKOUT1_DIVIDE=8, o_CLKOUT1=rtio_clk,
p_CLKOUT2_DIVIDE=4, o_CLKOUT2=rtiox_clk,
),
Instance("BUFG", name="rtioserdes_bufg_fb",
i_I=clkfbout, o_O=clkfbin),
Instance("BUFG", name="rtioserdes_bufg_div",
i_I=rtio_clk, o_O=self.cd_rtio_serdes.clk),
Instance("BUFG", name="rtioserdes_bufg",
i_I=rtiox_clk, o_O=self.cd_rtiox_serdes.clk)
]
self.comb += self.cd_rtio_serdes.rst.eq(ResetSignal("rio_phy"))
platform.add_platform_command(
"set_property CLOCK_DELAY_GROUP RTIOSERDES_BALANCE [get_nets -of [get_pins rtioserdes_bufg_fb/O]]")
platform.add_platform_command(
"set_property CLOCK_DELAY_GROUP RTIOSERDES_BALANCE [get_nets -of [get_pins rtioserdes_bufg_div/O]]")
platform.add_platform_command(
"set_property CLOCK_DELAY_GROUP RTIOSERDES_BALANCE [get_nets -of [get_pins rtioserdes_bufg/O]]")
platform.add_platform_command(
"set_property USER_CLOCK_ROOT X2Y1 [get_nets -of [get_pins rtioserdes_bufg_fb/O]]")
platform.add_platform_command(
"set_property USER_CLOCK_ROOT X2Y1 [get_nets -of [get_pins rtioserdes_bufg_div/O]]")
platform.add_platform_command(
"set_property USER_CLOCK_ROOT X2Y1 [get_nets -of [get_pins rtioserdes_bufg/O]]")
class Standalone(MiniSoC, AMPSoC):
mem_map = {
"cri_con": 0x10000000,
@ -239,7 +191,6 @@ class Standalone(MiniSoC, AMPSoC):
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
# RTIO
self.submodules.rtio_clkmul = _RTIOClockMultiplier(platform, 150e6)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
@ -247,12 +198,12 @@ class Standalone(MiniSoC, AMPSoC):
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
@ -390,7 +341,6 @@ class Master(MiniSoC, AMPSoC):
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gth.rxoutclk)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(platform, rtio_clk_freq)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
@ -398,12 +348,12 @@ class Master(MiniSoC, AMPSoC):
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
@ -455,12 +405,12 @@ class Satellite(BaseSoC):
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))