From 314d9b5d063c466a91f106e0fce3b191834910d5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 8 Oct 2019 12:59:52 +0800 Subject: [PATCH] kasli: default to 125MHz frequency for DRTIO This is the consistent and most common option. Sayma will also eventually move to it. --- artiq/gateware/targets/kasli.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 835f6c863..630108088 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -273,7 +273,7 @@ class MasterBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, rtio_clk_freq=150e6, enable_sata=False, **kwargs): + def __init__(self, rtio_clk_freq=125e6, enable_sata=False, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -435,7 +435,7 @@ class SatelliteBase(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, rtio_clk_freq=150e6, enable_sata=False, **kwargs): + def __init__(self, rtio_clk_freq=125e6, enable_sata=False, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon",