From 30dffb6644da766fd11f7bf5813cdf1b3763f492 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 15 Apr 2015 20:39:40 +0800 Subject: [PATCH] rtio/phy: add wishbone adapter --- artiq/gateware/rtio/phy/wishbone.py | 42 +++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 artiq/gateware/rtio/phy/wishbone.py diff --git a/artiq/gateware/rtio/phy/wishbone.py b/artiq/gateware/rtio/phy/wishbone.py new file mode 100644 index 000000000..0d9d06e24 --- /dev/null +++ b/artiq/gateware/rtio/phy/wishbone.py @@ -0,0 +1,42 @@ +from migen.fhdl.std import * + +from artiq.gateware.rtio import rtlink + + +class RT2WB(Module): + def __init__(self, wb, address_width, o_latency=0, i_latency=0): + self.rtlink = rtlink.Interface( + rtlink.OInterface( + flen(wb.dat_w), + address_width + 1, + latency=o_latency, + suppress_nop=False), + rtlink.IInterface( + flen(wb.dat_r), + timestamped=False, + latency=i_latency) + ) + + # # # + + active = Signal() + self.sync.rio += [ + If(self.rtlink.o.stb, + active.eq(1), + wb.adr.eq(self.rtlink.o.address[:address_width]), + wb.we.eq(~self.rtlink.o.address[address_width]), + wb.dat_w.eq(self.rtlink.o.data), + wb.sel.eq(2**flen(wb.sel) - 1) + ), + If(wb.ack, + active.eq(0) + ) + ] + self.comb += [ + self.rtlink.o.busy.eq(active), + wb.cyc.eq(active), + wb.stb.eq(active), + + self.i.stb.eq(wb.ack & ~wb.we), + self.i.data.eq(wb.dat_r) + ]