forked from M-Labs/artiq
suservo: lots of gateware/ runtime changes
tested/validated: * servo enable/disable * dds interface, timing, io_update, mask_nu * channel control (en_out, en_iir, profile) * profile configuration (coefficients, delays, offsets, channel) * adc timings and waveforms measured * asf state readback * adc readback individual changes below: suservo: correct rtio readback suservo: example, device_db [wip] suservo: change rtio channel layout suservo: mem ports in rio domain suservo: sck clocked from rio_phy suservo: cleanup, straighten out timing suservo: dds cs polarity suservo: simplify pipeline suservo: drop unused eem names suservo: decouple adc SR from IIR suservo: expand coredevice layer suservo: start the correct stage suservo: actually load ctrl suservo: refactor/tweak adc timing suservo: implement cpld and dds init
This commit is contained in:
parent
01f762a8f5
commit
307cd07b9d
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@ -0,0 +1,132 @@
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from artiq.language.core import kernel, delay, portable, now_mu
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from artiq.language.units import us, ms
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from numpy import int32, int64
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice import urukul, sampler
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COEFF_WIDTH = 18
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COEFF_DEPTH = 10 + 1
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WE = 1 << COEFF_DEPTH + 1
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STATE_SEL = 1 << COEFF_DEPTH
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CONFIG_SEL = 1 << COEFF_DEPTH - 1
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CONFIG_ADDR = CONFIG_SEL | STATE_SEL
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class SUServo:
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kernel_invariants = {"channel", "core", "pgia", "cpld0", "cpld1",
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"dds0", "dds1", "ref_period_mu"}
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def __init__(self, dmgr, channel, pgia_device,
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cpld0_device, cpld1_device,
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dds0_device, dds1_device,
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core_device="core"):
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self.core = dmgr.get(core_device)
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self.pgia = dmgr.get(pgia_device)
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self.dds0 = dmgr.get(dds0_device)
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self.dds1 = dmgr.get(dds1_device)
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self.cpld0 = dmgr.get(cpld0_device)
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self.cpld1 = dmgr.get(cpld1_device)
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self.channel = channel
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self.gains = 0x0000
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self.ref_period_mu = self.core.seconds_to_mu(
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self.core.coarse_ref_period)
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assert self.ref_period_mu == self.core.ref_multiplier
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@kernel
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def init(self):
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self.set_config(0)
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delay(2*us) # pipeline flush
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self.pgia.set_config_mu(
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sampler.SPI_CONFIG | spi.SPI_END,
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16, 4, sampler.SPI_CS_PGIA)
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self.cpld0.init(blind=True)
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cfg0 = self.cpld0.cfg_reg
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self.cpld0.cfg_write(cfg0 | (0xf << urukul.CFG_MASK_NU))
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self.dds0.init(blind=True)
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self.cpld0.cfg_write(cfg0)
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self.cpld1.init(blind=True)
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cfg1 = self.cpld1.cfg_reg
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self.cpld1.cfg_write(cfg1 | (0xf << urukul.CFG_MASK_NU))
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self.dds1.init(blind=True)
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self.cpld1.cfg_write(cfg1)
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@kernel
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def write(self, addr, value):
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rtio_output(now_mu(), self.channel, addr | WE, value)
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delay_mu(self.ref_period_mu)
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@kernel
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def read(self, addr):
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rtio_output(now_mu(), self.channel, addr, 0)
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return rtio_input_data(self.channel)
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@kernel
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def set_config(self, start):
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self.write(CONFIG_ADDR, start)
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@kernel
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def get_status(self):
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return self.read(CONFIG_ADDR)
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@kernel
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def get_adc_mu(self, adc):
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return self.read(STATE_SEL | (adc << 1) | (1 << 8))
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@kernel
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def set_gain_mu(self, channel, gain):
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"""Set instrumentation amplifier gain of a channel.
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The four gain settings (0, 1, 2, 3) corresponds to gains of
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(1, 10, 100, 1000) respectively.
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:param channel: Channel index
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:param gain: Gain setting
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"""
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gains = self.gains
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gains &= ~(0b11 << (channel*2))
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gains |= gain << (channel*2)
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self.pgia.write(gains << 16)
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self.gains = gains
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class Channel:
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kernel_invariants = {"channel", "core", "servo", "servo_channel"}
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def __init__(self, dmgr, channel, servo_device,
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core_device="core"):
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self.core = dmgr.get(core_device)
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self.servo = dmgr.get(servo_device)
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self.channel = channel
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self.servo_channel = self.channel + 8 - self.servo.channel # FIXME
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@kernel
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def set(self, en_out, en_iir=0, profile=0):
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rtio_output(now_mu(), self.channel, 0,
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en_out | (en_iir << 1) | (profile << 2))
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@kernel
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def set_profile_mu(self, profile, ftw, adc, offset,
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a1, b0, b1, delay, pow=0):
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base = (self.servo_channel << 8) | (profile << 3)
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data = [ftw >> 16, b1, pow, adc | (delay << 8), offset, a1, ftw, b0]
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for i in range(8):
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self.servo.write(base + i, data[i])
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@kernel
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def get_profile_mu(self, profile, data):
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base = (self.servo_channel << 8) | (profile << 3)
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for i in range(8):
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data[i] = self.servo.read(base + i)
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delay(2*us)
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@kernel
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def get_asf_mu(self, profile):
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return self.servo.read(STATE_SEL | (self.servo_channel << 5) | profile)
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@ -1,4 +1,4 @@
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core_addr = "lauda.ber.quartiq.de"
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core_addr = "10.0.16.119"
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device_db = {
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"core": {
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@ -141,9 +141,11 @@ device_db = {
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"class": "SUServo",
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"arguments": {
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"channel": 24,
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"sampler_pgia_device": "spi_sampler0_pgia",
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"urukul0_device": "urukul0_cpld",
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"urukul1_device": "urukul1_cpld"
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"pgia_device": "spi_sampler0_pgia",
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"cpld0_device": "urukul0_cpld",
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"cpld1_device": "urukul1_cpld",
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"dds0_device": "urukul0_dds",
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"dds1_device": "urukul1_dds"
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}
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},
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@ -215,10 +217,20 @@ device_db = {
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul0",
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"refclk": 125e6,
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"refclk": 100e6,
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"clk_sel": 0
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}
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},
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"urukul0_dds": {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 40,
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"chip_select": 3,
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"cpld_device": "urukul0_cpld",
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}
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},
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"spi_urukul1": {
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"type": "local",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul1",
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"refclk": 125e6,
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"refclk": 100e6,
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"clk_sel": 0
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}
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},
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"urukul1_dds": {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 40,
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"chip_select": 3,
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"cpld_device": "urukul1_cpld",
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}
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},
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"led0": {
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"type": "local",
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@ -1,35 +0,0 @@
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from artiq.experiment import *
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class Sampler(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("sampler0")
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def run(self):
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self.data = []
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self.sample()
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for d in self.data:
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print(d)
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@kernel
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def sample(self):
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self.core.break_realtime()
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self.sampler0.init()
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for g in range(4):
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for ch in range(8):
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self.sampler0.set_gain_mu(ch, g)
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self.ret([self.sampler0.get_gains_mu()])
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delay(10*ms)
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raw = [0] * 8
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self.sampler0.sample_mu(raw)
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self.ret(raw)
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delay(10*ms)
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data = [0.] * 8
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self.sampler0.sample(data)
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self.ret(data)
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delay(10*ms)
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@rpc(flags={"async"})
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def ret(self, data):
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self.data.append(data)
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@ -0,0 +1,33 @@
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from artiq.experiment import *
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class SUServo(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("led0")
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self.setattr_device("suservo0")
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self.setattr_device("suservo0_ch0")
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def run(self):
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# self.led()
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self.init()
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@kernel
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def init(self):
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self.core.break_realtime()
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self.core.reset()
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self.suservo0.init()
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self.suservo0.set_config(1)
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print(self.suservo0.get_status())
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delay(3*ms)
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self.suservo0.set_config(0)
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delay(3*ms)
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print(self.suservo0.get_status())
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@kernel
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def led(self):
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self.core.break_realtime()
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for i in range(10):
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self.led0.pulse(.1*s)
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delay(.1*s)
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@ -7,18 +7,19 @@ class RTServoCtrl(Module):
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"""Per channel RTIO control interface"""
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def __init__(self, ctrl):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(len(ctrl)))
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rtlink.OInterface(len(ctrl.profile) + 2))
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# # #
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self.sync.rio += [
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If(self.rtlink.o.stb,
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Cat(ctrl.profile, ctrl.en_out, ctrl.en_iir).eq(
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self.rtlink.o.data),
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)
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]
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self.comb += [
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ctrl.stb.eq(self.rtlink.o.stb)
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ctrl.stb.eq(self.rtlink.o.stb),
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self.rtlink.o.busy.eq(0)
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]
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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Cat(ctrl.en_out, ctrl.en_iir, ctrl.profile).eq(
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self.rtlink.o.data)
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)
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]
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@ -26,10 +27,11 @@ class RTServoMem(Module):
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"""All-channel all-profile coefficient and state RTIO control
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interface."""
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def __init__(self, w, servo):
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m_coeff = servo.m_coeff.get_port(write_capable=True,
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we_granularity=w.coeff)
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m_coeff = servo.iir.m_coeff.get_port(write_capable=True,
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we_granularity=w.coeff, clock_domain="rio")
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assert len(m_coeff.we) == 2
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m_state = servo.m_state.get_port(write_capable=True)
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m_state = servo.iir.m_state.get_port(write_capable=True,
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clock_domain="rio")
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self.specials += m_state, m_coeff
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# just expose the w.coeff (18) MSBs of state
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@ -52,8 +54,8 @@ class RTServoMem(Module):
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# # #
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config = Signal(1, reset=0)
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status = Signal(2)
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config = Signal(w.coeff, reset=0)
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status = Signal(w.coeff)
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self.comb += [
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Cat(servo.start).eq(config),
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status.eq(Cat(servo.start, servo.done))
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@ -87,16 +89,18 @@ class RTServoMem(Module):
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m_state.we.eq(self.rtlink.o.stb & we & state_sel & ~config_sel),
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]
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read = Signal()
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read_sel = Signal()
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read_state = Signal()
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read_high = Signal()
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read_config = Signal()
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self.sync.rio += [
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If(read,
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read.eq(0)
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),
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If(self.rtlink.o.stb,
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read.eq(~we),
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read_sel.eq(state_sel),
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read_state.eq(state_sel),
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read_high.eq(high_coeff),
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read_config.eq(config_sel),
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)
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]
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self.sync.rio_phy += [
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@ -107,8 +111,8 @@ class RTServoMem(Module):
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self.comb += [
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self.rtlink.i.stb.eq(read),
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self.rtlink.i.data.eq(
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Mux(state_sel,
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Mux(config_sel,
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Mux(read_state,
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Mux(read_config,
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status,
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m_state.dat_r[w.state - w.coeff:]),
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Mux(read_high,
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@ -55,13 +55,13 @@ class ADC(Module):
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assert p.lanes*t_read == p.width*p.channels
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assert all(_ > 0 for _ in (p.t_cnvh, p.t_conv, p.t_rtt))
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assert p.t_conv > 1
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count = Signal(max=max(p.t_cnvh, p.t_conv - 1, t_read, p.t_rtt + 1) - 1,
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count = Signal(max=max(p.t_cnvh, p.t_conv, t_read, p.t_rtt),
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reset_less=True)
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count_load = Signal.like(count)
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count_done = Signal()
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self.comb += [
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count_done.eq(count == 0),
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]
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update = Signal()
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self.comb += count_done.eq(count == 0)
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self.sync += [
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count.eq(count - 1),
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If(count_done,
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@ -78,7 +78,7 @@ class ADC(Module):
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)
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)
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fsm.act("CNVH",
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count_load.eq(p.t_conv - 2), # account for sck ODDR delay
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count_load.eq(p.t_conv - 1),
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pads.cnv.eq(1),
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If(count_done,
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NextState("CONV")
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@ -92,7 +92,7 @@ class ADC(Module):
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)
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fsm.act("READ",
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self.reading.eq(1),
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count_load.eq(p.t_rtt), # again account for sck ODDR delay
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count_load.eq(p.t_rtt - 1),
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pads.sck_en.eq(1),
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If(count_done,
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NextState("RTT")
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@ -101,6 +101,7 @@ class ADC(Module):
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fsm.act("RTT", # account for sck->clkout round trip time
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self.reading.eq(1),
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If(count_done,
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update.eq(1),
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NextState("IDLE")
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)
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)
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@ -111,10 +112,7 @@ class ADC(Module):
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sck_en_ret = 1
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self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
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self.comb += [
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# falling clkout makes two bits available
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self.cd_ret.clk.eq(pads.clkout)
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]
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self.comb += self.cd_ret.clk.eq(pads.clkout)
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k = p.channels//p.lanes
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assert t_read == k*p.width
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@ -126,7 +124,9 @@ class ADC(Module):
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sdo_sr[0].eq(sdo),
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)
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]
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self.comb += [
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self.sync += [
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If(update,
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Cat(reversed([self.data[i*k + j] for j in range(k)])
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).eq(sdo_sr)
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)
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]
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|
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@ -36,13 +36,8 @@ class DDS(spi.SPISimple):
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)
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]
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io_update = pads.io_update
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# this assumes that the cycle time (1/125 MHz = 8 ns) is >1 SYNC_CLK
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# cycle (1/250 MHz = 4ns)
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done = Signal()
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self.sync += [
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done.eq(self.done)
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]
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self.comb += [
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io_update.eq(self.done & ~done)
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]
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done_old = Signal()
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self.sync += done_old.eq(self.done)
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self.comb += pads.io_update.eq(self.done & ~done_old)
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|
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@ -3,17 +3,17 @@ from migen.genlib.io import DifferentialOutput, DifferentialInput, DDROutput
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class SamplerPads(Module):
|
||||
def __init__(self, platform, eem0, eem1):
|
||||
def __init__(self, platform, eem):
|
||||
self.sck_en = Signal()
|
||||
self.cnv = Signal()
|
||||
self.clkout = Signal()
|
||||
|
||||
spip = platform.request("{}_adc_spi_p".format(eem0))
|
||||
spin = platform.request("{}_adc_spi_n".format(eem0))
|
||||
cnv = platform.request("{}_cnv".format(eem0))
|
||||
sdr = platform.request("{}_sdr".format(eem0))
|
||||
dp = platform.request("{}_adc_data_p".format(eem0))
|
||||
dn = platform.request("{}_adc_data_n".format(eem0))
|
||||
spip = platform.request("{}_adc_spi_p".format(eem))
|
||||
spin = platform.request("{}_adc_spi_n".format(eem))
|
||||
cnv = platform.request("{}_cnv".format(eem))
|
||||
sdr = platform.request("{}_sdr".format(eem))
|
||||
dp = platform.request("{}_adc_data_p".format(eem))
|
||||
dn = platform.request("{}_adc_data_n".format(eem))
|
||||
|
||||
clkout_se = Signal()
|
||||
sck = Signal()
|
||||
|
|
@ -21,7 +21,7 @@ class SamplerPads(Module):
|
|||
self.specials += [
|
||||
DifferentialOutput(self.cnv, cnv.p, cnv.n),
|
||||
DifferentialOutput(1, sdr.p, sdr.n),
|
||||
DDROutput(self.sck_en, 0, sck),
|
||||
DDROutput(0, self.sck_en, sck, ClockSignal("rio_phy")),
|
||||
DifferentialOutput(sck, spip.clk, spin.clk),
|
||||
DifferentialInput(dp.clkout, dn.clkout, clkout_se),
|
||||
Instance("BUFR", i_I=clkout_se, o_O=self.clkout)
|
||||
|
|
@ -52,17 +52,17 @@ class SamplerPads(Module):
|
|||
|
||||
|
||||
class UrukulPads(Module):
|
||||
def __init__(self, platform, eem00, eem01, eem10, eem11):
|
||||
def __init__(self, platform, eem0, eem1):
|
||||
spip, spin = [[
|
||||
platform.request("{}_qspi_{}".format(eem, pol), 0)
|
||||
for eem in (eem00, eem10)] for pol in "pn"]
|
||||
for eem in (eem0, eem1)] for pol in "pn"]
|
||||
ioup = [platform.request("{}_io_update".format(eem), 0)
|
||||
for eem in (eem00, eem10)]
|
||||
for eem in (eem0, eem1)]
|
||||
self.cs_n = Signal()
|
||||
self.clk = Signal()
|
||||
self.io_update = Signal()
|
||||
self.specials += [(
|
||||
DifferentialOutput(self.cs_n, spip[i].cs_n, spin[i].cs_n),
|
||||
DifferentialOutput(~self.cs_n, spip[i].cs, spin[i].cs),
|
||||
DifferentialOutput(self.clk, spip[i].clk, spin[i].clk),
|
||||
DifferentialOutput(self.io_update, ioup[i].p, ioup[i].n))
|
||||
for i in range(2)]
|
||||
|
|
|
|||
|
|
@ -24,38 +24,37 @@ class Servo(Module):
|
|||
assert t_iir + (2 << iir_p.channel) < t_cycle, "need shifting time"
|
||||
|
||||
self.start = Signal()
|
||||
t_restart = t_cycle - t_adc
|
||||
t_restart = t_cycle - t_adc + 1
|
||||
assert t_restart > 0
|
||||
cnt = Signal(max=t_restart + 1)
|
||||
cnt = Signal(max=t_restart)
|
||||
cnt_done = Signal()
|
||||
token = Signal(2)
|
||||
active = Signal(3)
|
||||
self.done = Signal()
|
||||
iir_done = Signal()
|
||||
self.comb += [
|
||||
cnt_done.eq(cnt == 0),
|
||||
iir_done.eq(self.iir.shifting | self.iir.done),
|
||||
self.adc.start.eq(self.start & cnt_done),
|
||||
self.iir.start.eq(token[0] & self.adc.done),
|
||||
self.dds.start.eq(token[1] & iir_done),
|
||||
self.done.eq(self.dds.done),
|
||||
]
|
||||
self.sync += [
|
||||
If(self.adc.done & ~cnt_done,
|
||||
cnt.eq(cnt - 1),
|
||||
If(self.dds.done,
|
||||
active[2].eq(0)
|
||||
),
|
||||
If(self.adc.start,
|
||||
cnt.eq(t_restart),
|
||||
If(self.dds.start & self.dds.done,
|
||||
active[2].eq(1),
|
||||
active[1].eq(0)
|
||||
),
|
||||
If(self.adc.done,
|
||||
token[0].eq(0)
|
||||
If(self.iir.start & self.iir.done,
|
||||
active[1].eq(1),
|
||||
active[0].eq(0)
|
||||
),
|
||||
If(self.adc.start,
|
||||
token[0].eq(1)
|
||||
If(~cnt_done & self.adc.done,
|
||||
cnt.eq(cnt - 1)
|
||||
),
|
||||
If(iir_done,
|
||||
token[1].eq(0)
|
||||
),
|
||||
If(self.iir.start,
|
||||
token[1].eq(1)
|
||||
If(self.adc.start & self.adc.done,
|
||||
active[0].eq(1),
|
||||
cnt.eq(t_restart - 1)
|
||||
)
|
||||
]
|
||||
self.comb += [
|
||||
cnt_done.eq(cnt == 0),
|
||||
self.adc.start.eq(self.start & cnt_done),
|
||||
self.iir.start.eq(active[0] & self.adc.done),
|
||||
self.dds.start.eq(active[1] &
|
||||
(self.iir.shifting | self.iir.done)),
|
||||
self.done.eq(self.dds.done),
|
||||
]
|
||||
|
|
|
|||
|
|
@ -37,8 +37,6 @@ class SPISimple(Module):
|
|||
|
||||
assert p.clk >= 1
|
||||
|
||||
cs_n = pads.cs_n
|
||||
clk = pads.clk
|
||||
cnt = Signal(max=max(2, p.clk), reset_less=True)
|
||||
cnt_done = Signal()
|
||||
cnt_next = Signal()
|
||||
|
|
@ -54,21 +52,17 @@ class SPISimple(Module):
|
|||
]
|
||||
|
||||
for i, d in enumerate(self.data):
|
||||
self.comb += [
|
||||
getattr(pads, "mosi{}".format(i)).eq(d[-1])
|
||||
]
|
||||
self.comb += getattr(pads, "mosi{}".format(i)).eq(d[-1])
|
||||
|
||||
bits = Signal(max=p.width + 1, reset_less=True)
|
||||
|
||||
self.submodules.fsm = fsm = CEInserter()(FSM("IDLE"))
|
||||
|
||||
self.comb += [
|
||||
fsm.ce.eq(cnt_done)
|
||||
]
|
||||
self.comb += fsm.ce.eq(cnt_done)
|
||||
|
||||
fsm.act("IDLE",
|
||||
self.done.eq(1),
|
||||
cs_n.eq(1),
|
||||
pads.cs_n.eq(1),
|
||||
If(self.start,
|
||||
cnt_next.eq(1),
|
||||
NextState("SETUP")
|
||||
|
|
@ -84,7 +78,7 @@ class SPISimple(Module):
|
|||
)
|
||||
fsm.act("HOLD",
|
||||
cnt_next.eq(1),
|
||||
clk.eq(1),
|
||||
pads.clk.eq(1),
|
||||
NextState("SETUP")
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -362,7 +362,7 @@ def _urukul_qspi(eem0, eem1):
|
|||
))
|
||||
ios += [
|
||||
("{}_qspi_p".format(eem0), 0,
|
||||
Subsignal("cs_n", Pins(_eem_pin(eem0, 5, "p"))),
|
||||
Subsignal("cs", Pins(_eem_pin(eem0, 5, "p"))),
|
||||
Subsignal("clk", Pins(_eem_pin(eem0, 2, "p"))),
|
||||
Subsignal("mosi0", Pins(_eem_pin(eem1, 0, "p"))),
|
||||
Subsignal("mosi1", Pins(_eem_pin(eem1, 1, "p"))),
|
||||
|
|
@ -371,7 +371,7 @@ def _urukul_qspi(eem0, eem1):
|
|||
IOStandard("LVDS_25"),
|
||||
),
|
||||
("{}_qspi_n".format(eem0), 0,
|
||||
Subsignal("cs_n", Pins(_eem_pin(eem0, 5, "n"))),
|
||||
Subsignal("cs", Pins(_eem_pin(eem0, 5, "n"))),
|
||||
Subsignal("clk", Pins(_eem_pin(eem0, 2, "n"))),
|
||||
Subsignal("mosi0", Pins(_eem_pin(eem1, 0, "n"))),
|
||||
Subsignal("mosi1", Pins(_eem_pin(eem1, 1, "n"))),
|
||||
|
|
@ -525,25 +525,25 @@ class SUServo(_StandaloneBase):
|
|||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
# EEM3, EEM2: Sampler
|
||||
sampler_pads = servo_pads.SamplerPads(self.platform, "eem3", "eem2")
|
||||
sampler_pads = servo_pads.SamplerPads(self.platform, "eem3")
|
||||
# EEM5, EEM4 and EEM7, EEM6: Urukul
|
||||
urukul_pads = servo_pads.UrukulPads(self.platform,
|
||||
"eem5", "eem4", "eem7", "eem6")
|
||||
adc_p = servo.ADCParams(width=16, channels=8, lanes=4,
|
||||
t_cnvh=4, t_conv=57, t_rtt=4)
|
||||
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16,
|
||||
asf=14, word=16, accu=48, shift=11,
|
||||
channel=3, profile=5)
|
||||
"eem5", "eem7")
|
||||
adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4,
|
||||
# account for SCK pipeline latency
|
||||
t_conv=57 - 4, t_rtt=4 + 4)
|
||||
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
|
||||
accu=48, shift=11, channel=3, profile=5)
|
||||
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
|
||||
channels=adc_p.channels, clk=1)
|
||||
su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
|
||||
su = ClockDomainsRenamer({"sys": "rio_phy"})(su)
|
||||
su = ClockDomainsRenamer("rio_phy")(su)
|
||||
self.submodules += sampler_pads, urukul_pads, su
|
||||
|
||||
ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
|
||||
self.submodules += ctrls
|
||||
rtio_channels.extend(rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
|
||||
mem = rtservo.RTServoMem(iir_p, su.iir)
|
||||
mem = rtservo.RTServoMem(iir_p, su)
|
||||
self.submodules += mem
|
||||
rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ class TB(Module):
|
|||
sr = Signal(p.width*p.channels//p.lanes, reset_less=True)
|
||||
srs.append(sr)
|
||||
self.sync.adc += [
|
||||
sdo.eq(self._dly(sr[-1], -1)),
|
||||
sdo.eq(self._dly(sr[-1], 0)),
|
||||
If(adc_sck_en,
|
||||
sr[1:].eq(sr)
|
||||
)
|
||||
|
|
@ -52,10 +52,10 @@ class TB(Module):
|
|||
|
||||
adc_clk_rec = Signal()
|
||||
self.comb += [
|
||||
adc_sck_en.eq(self._dly(self.sck_en, 1)),
|
||||
adc_sck_en.eq(self._dly(self.sck_en, 0)),
|
||||
self.sck_en_ret.eq(self._dly(adc_sck_en)),
|
||||
|
||||
adc_clk_rec.eq(self._dly(self.sck, 1)),
|
||||
adc_clk_rec.eq(self._dly(self.sck, 0)),
|
||||
self.clkout.eq(self._dly(adc_clk_rec)),
|
||||
]
|
||||
|
||||
|
|
|
|||
|
|
@ -11,10 +11,9 @@ from artiq.gateware.suservo import servo
|
|||
class ServoSim(servo.Servo):
|
||||
def __init__(self):
|
||||
adc_p = servo.ADCParams(width=16, channels=8, lanes=4,
|
||||
t_cnvh=4, t_conv=57, t_rtt=4)
|
||||
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16,
|
||||
asf=14, word=16, accu=48, shift=11,
|
||||
channel=3, profile=5)
|
||||
t_cnvh=4, t_conv=57 - 4, t_rtt=4 + 4)
|
||||
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
|
||||
accu=48, shift=11, channel=3, profile=5)
|
||||
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
|
||||
channels=adc_p.channels, clk=1)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue