forked from M-Labs/artiq
Fix whitespace.
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@ -81,7 +81,7 @@ class _RTIOCRG(Module, AutoCSR):
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# The default user SMA voltage on KC705 is 2.5V, and the Migen platform
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# follows this default. But since the SMAs are on the same bank as the DDS,
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# which is set to 3.3V by reprogramming the KC705 power ICs, we need to
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# redefine them here.
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# redefine them here.
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_sma33_io = [
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("user_sma_gpio_p_33", 0, Pins("Y23"), IOStandard("LVCMOS33")),
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("user_sma_gpio_n_33", 0, Pins("Y24"), IOStandard("LVCMOS33")),
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@ -293,7 +293,7 @@ class NIST_CLOCK(_NIST_Ions):
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class NIST_QC2(_NIST_Ions):
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 24 DDS channels. Two backplanes are used.
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and 24 DDS channels. Two backplanes are used.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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@ -310,19 +310,19 @@ class NIST_QC2(_NIST_Ions):
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platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# CLK0, CLK1 are for clock generators, on backplane SMP connectors
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for i in range(2):
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for i in range(2):
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phy = ttl_simple.ClockGen(
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platform.request("clkout", i))
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self.submodules += phy
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clock_generators.append(rtio.Channel.from_phy(phy))
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clock_generators.append(rtio.Channel.from_phy(phy))
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# user SMA on KC705 board
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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