From 2edf65f57b86fa9797d5f9cb300191cec31e50ba Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 13 Mar 2018 00:20:57 +0800 Subject: [PATCH] drtio: fix satellite minimum_coarse_timestamp clock domain (#947) --- artiq/gateware/drtio/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py index 36f262c4f..ff64bf5f0 100644 --- a/artiq/gateware/drtio/core.py +++ b/artiq/gateware/drtio/core.py @@ -97,7 +97,7 @@ class DRTIOSatellite(Module): enable_spread=False, report_buffer_space=True, interface=self.rt_packet.cri)) self.comb += self.outputs.coarse_timestamp.eq(coarse_ts) - self.sync += self.outputs.minimum_coarse_timestamp.eq(coarse_ts + 16) + self.sync.rtio += self.outputs.minimum_coarse_timestamp.eq(coarse_ts + 16) self.submodules.inputs = ClockDomainsRenamer("rio")( InputCollector(channels, fine_ts_width, "sync",