forked from M-Labs/artiq
sayma_amc: si5324_clkout -> cdr_clk_clean
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af785b9a9c
commit
2ec5a58c59
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@ -154,7 +154,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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self.config["SI5324_SAYMA_REF"] = None
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self.config["SI5324_SAYMA_REF"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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# ensure pins are properly biased and terminated
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# ensure pins are properly biased and terminated
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si5324_clkout = platform.request("si5324_clkout", 0)
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si5324_clkout = platform.request("cdr_clk_clean", 0)
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self.specials += Instance(
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self.specials += Instance(
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"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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attr={("DONT_TOUCH", "true")})
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attr={("DONT_TOUCH", "true")})
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@ -351,7 +351,7 @@ class Master(MiniSoC, AMPSoC):
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for i in range(2)
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for i in range(2)
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]
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout", 0),
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clock_pads=platform.request("cdr_clk_clean", 0),
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data_pads=[platform.request("sfp", i) for i in range(2)] +
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data_pads=[platform.request("sfp", i) for i in range(2)] +
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[platform.request("rtm_gth", i) for i in range(8)],
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[platform.request("rtm_gth", i) for i in range(8)],
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sys_clk_freq=self.clk_freq,
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sys_clk_freq=self.clk_freq,
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@ -524,7 +524,7 @@ class Satellite(BaseSoC, RTMCommon):
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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clock_pads=platform.request("cdr_clk_clean"),
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data_pads=[platform.request("sfp", 0)],
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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rtio_clk_freq=rtio_clk_freq)
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