forked from M-Labs/artiq
rtio/wishbone: make replace configurable
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parent
03b53c3af9
commit
2e39802a61
@ -5,7 +5,7 @@ from artiq.gateware.rtio import rtlink
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class RT2WB(Module):
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def __init__(self, address_width, wb=None):
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def __init__(self, address_width, wb=None, rtio_enable_replace=False):
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if wb is None:
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wb = wishbone.Interface()
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self.wb = wb
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@ -14,7 +14,7 @@ class RT2WB(Module):
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len(wb.dat_w),
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address_width + 1,
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suppress_nop=False,
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enable_replace=False),
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enable_replace=rtio_enable_replace),
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rtlink.IInterface(
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len(wb.dat_r),
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timestamped=False)
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