forked from M-Labs/artiq
firmware: rewrite cache flushing code in Rust.
This commit is contained in:
parent
209be73204
commit
2de3770c06
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@ -0,0 +1,44 @@
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use spr::{self, mfspr, mtspr};
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use csr;
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use mem;
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pub fn flush_cpu_icache() {
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unsafe {
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let iccfgr = mfspr(spr::SPR_ICCFGR);
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let ways = 1 << (iccfgr & spr::SPR_ICCFGR_NCW);
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let set_size = 1 << ((iccfgr & spr::SPR_ICCFGR_NCS) >> 3);
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let block_size = if iccfgr & spr::SPR_ICCFGR_CBS != 0 { 32 } else { 16 };
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let size = set_size * ways * block_size;
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let mut i = 0;
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while i < size {
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mtspr(spr::SPR_ICBIR, i);
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i += block_size;
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}
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}
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}
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pub fn flush_cpu_dcache() {
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unsafe {
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let dccfgr = mfspr(spr::SPR_DCCFGR);
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let ways = 1 << (dccfgr & spr::SPR_ICCFGR_NCW);
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let set_size = 1 << ((dccfgr & spr::SPR_DCCFGR_NCS) >> 3);
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let block_size = if dccfgr & spr::SPR_DCCFGR_CBS != 0 { 32 } else { 16 };
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let size = set_size * ways * block_size;
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let mut i = 0;
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while i < size {
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mtspr(spr::SPR_DCBIR, i);
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i += block_size;
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}
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}
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}
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pub fn flush_l2_cache() {
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unsafe {
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for i in 0..2 * (csr::CONFIG_L2_SIZE as usize) / 4 {
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let addr = mem::MAIN_RAM_BASE + i * 4;
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asm!("l.lwz r0, 0($1)"::"r"(addr):"r0":"volatile")
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}
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}
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}
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@ -10,6 +10,7 @@ include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
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pub mod spr;
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pub mod irq;
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pub mod cache;
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pub mod clock;
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pub mod uart;
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#[cfg(feature = "uart_console")]
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@ -34,11 +35,6 @@ pub mod ad9154;
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#[cfg(feature = "uart_console")]
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pub use uart_console::Console;
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extern {
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pub fn flush_cpu_dcache();
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pub fn flush_l2_cache();
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}
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pub fn ident(buf: &mut [u8]) -> &str {
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unsafe {
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let len = ptr::read_volatile(csr::IDENTIFIER_MEM_BASE);
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@ -57,6 +57,28 @@ pub const SPR_ESR_BASE: u32 = SPRGROUP_SYS + 64;
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pub const SPR_ESR_LAST: u32 = SPRGROUP_SYS + 79;
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pub const SPR_GPR_BASE: u32 = SPRGROUP_SYS + 1024;
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/* Data MMU group */
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pub const SPR_DMMUCR: u32 = SPRGROUP_DMMU + 0;
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pub const SPR_DTLBEIR: u32 = SPRGROUP_DMMU + 2;
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/* Instruction MMU group */
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pub const SPR_IMMUCR: u32 = SPRGROUP_IMMU + 0;
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pub const SPR_ITLBEIR: u32 = SPRGROUP_IMMU + 2;
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/* Data cache group */
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pub const SPR_DCCR: u32 = SPRGROUP_DC + 0;
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pub const SPR_DCBPR: u32 = SPRGROUP_DC + 1;
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pub const SPR_DCBFR: u32 = SPRGROUP_DC + 2;
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pub const SPR_DCBIR: u32 = SPRGROUP_DC + 3;
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pub const SPR_DCBWR: u32 = SPRGROUP_DC + 4;
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pub const SPR_DCBLR: u32 = SPRGROUP_DC + 5;
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/* Instruction cache group */
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pub const SPR_ICCR: u32 = SPRGROUP_IC + 0;
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pub const SPR_ICBPR: u32 = SPRGROUP_IC + 1;
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pub const SPR_ICBIR: u32 = SPRGROUP_IC + 2;
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pub const SPR_ICBLR: u32 = SPRGROUP_IC + 3;
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// [snip]
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/* PIC group */
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@ -89,3 +111,80 @@ pub const SPR_SR_FO: u32 = 0x00008000; /* Fixed one */
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pub const SPR_SR_SUMRA: u32 = 0x00010000; /* Supervisor SPR read access */
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pub const SPR_SR_RES: u32 = 0x0ffe0000; /* Reserved */
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pub const SPR_SR_CID: u32 = 0xf0000000; /* Context ID */
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/*
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* Bit definitions for Data Cache Control register
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*
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*/
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pub const SPR_DCCR_EW: u32 = 0x000000ff; /* Enable ways */
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/*
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* Bit definitions for Insn Cache Control register
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*
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*/
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pub const SPR_ICCR_EW: u32 = 0x000000ff; /* Enable ways */
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/*
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* Bit definitions for Data Cache Configuration Register
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*
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*/
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pub const SPR_DCCFGR_NCW: u32 = 0x00000007;
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pub const SPR_DCCFGR_NCS: u32 = 0x00000078;
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pub const SPR_DCCFGR_CBS: u32 = 0x00000080;
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pub const SPR_DCCFGR_CWS: u32 = 0x00000100;
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pub const SPR_DCCFGR_CCRI: u32 = 0x00000200;
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pub const SPR_DCCFGR_CBIRI: u32 = 0x00000400;
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pub const SPR_DCCFGR_CBPRI: u32 = 0x00000800;
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pub const SPR_DCCFGR_CBLRI: u32 = 0x00001000;
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pub const SPR_DCCFGR_CBFRI: u32 = 0x00002000;
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pub const SPR_DCCFGR_CBWBRI: u32 = 0x00004000;
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pub const SPR_DCCFGR_NCW_OFF: u32 = 0;
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pub const SPR_DCCFGR_NCS_OFF: u32 = 3;
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pub const SPR_DCCFGR_CBS_OFF: u32 = 7;
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/*
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* Bit definitions for Instruction Cache Configuration Register
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*
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*/
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pub const SPR_ICCFGR_NCW: u32 = 0x00000007;
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pub const SPR_ICCFGR_NCS: u32 = 0x00000078;
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pub const SPR_ICCFGR_CBS: u32 = 0x00000080;
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pub const SPR_ICCFGR_CCRI: u32 = 0x00000200;
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pub const SPR_ICCFGR_CBIRI: u32 = 0x00000400;
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pub const SPR_ICCFGR_CBPRI: u32 = 0x00000800;
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pub const SPR_ICCFGR_CBLRI: u32 = 0x00001000;
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pub const SPR_ICCFGR_NCW_OFF: u32 = 0;
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pub const SPR_ICCFGR_NCS_OFF: u32 = 3;
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pub const SPR_ICCFGR_CBS_OFF: u32 = 7;
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/*
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* Bit definitions for Data MMU Configuration Register
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*
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*/
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pub const SPR_DMMUCFGR_NTW: u32 = 0x00000003;
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pub const SPR_DMMUCFGR_NTS: u32 = 0x0000001C;
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pub const SPR_DMMUCFGR_NAE: u32 = 0x000000E0;
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pub const SPR_DMMUCFGR_CRI: u32 = 0x00000100;
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pub const SPR_DMMUCFGR_PRI: u32 = 0x00000200;
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pub const SPR_DMMUCFGR_TEIRI: u32 = 0x00000400;
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pub const SPR_DMMUCFGR_HTR: u32 = 0x00000800;
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pub const SPR_DMMUCFGR_NTW_OFF: u32 = 0;
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pub const SPR_DMMUCFGR_NTS_OFF: u32 = 2;
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/*
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* Bit definitions for Instruction MMU Configuration Register
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*
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*/
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pub const SPR_IMMUCFGR_NTW: u32 = 0x00000003;
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pub const SPR_IMMUCFGR_NTS: u32 = 0x0000001C;
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pub const SPR_IMMUCFGR_NAE: u32 = 0x000000E0;
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pub const SPR_IMMUCFGR_CRI: u32 = 0x00000100;
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pub const SPR_IMMUCFGR_PRI: u32 = 0x00000200;
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pub const SPR_IMMUCFGR_TEIRI: u32 = 0x00000400;
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pub const SPR_IMMUCFGR_HTR: u32 = 0x00000800;
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pub const SPR_IMMUCFGR_NTW_OFF: u32 = 0;
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pub const SPR_IMMUCFGR_NTS_OFF: u32 = 2;
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@ -1,5 +1,5 @@
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use std::io::{self, Write};
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use board::{self, csr};
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use board::{csr, cache};
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use sched::{Io, TcpSocket};
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use analyzer_proto::*;
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@ -35,8 +35,8 @@ fn disarm() {
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unsafe {
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csr::rtio_analyzer::enable_write(0);
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while csr::rtio_analyzer::busy_read() != 0 {}
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board::flush_cpu_dcache();
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board::flush_l2_cache();
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cache::flush_cpu_dcache();
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cache::flush_l2_cache();
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}
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}
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@ -1,7 +1,7 @@
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use core::ptr::{read_volatile, write_volatile};
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use board;
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use board::{mem, cache};
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const MAILBOX: *mut usize = board::mem::MAILBOX_BASE as *mut usize;
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const MAILBOX: *mut usize = mem::MAILBOX_BASE as *mut usize;
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static mut LAST: usize = 0;
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pub unsafe fn send(data: usize) {
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@ -23,7 +23,7 @@ pub fn receive() -> usize {
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0
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} else {
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if data != 0 {
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board::flush_cpu_dcache()
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cache::flush_cpu_dcache()
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}
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data
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}
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@ -2,10 +2,10 @@
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use core::ptr::{read_volatile, write_volatile};
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use core::slice;
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use board;
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use board::{mem, cache};
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const SEND_MAILBOX: *mut usize = (board::mem::MAILBOX_BASE + 4) as *mut usize;
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const RECV_MAILBOX: *mut usize = (board::mem::MAILBOX_BASE + 8) as *mut usize;
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const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 4) as *mut usize;
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const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 8) as *mut usize;
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const QUEUE_BEGIN: usize = 0x40400000;
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const QUEUE_END: usize = 0x407fff80;
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@ -51,7 +51,7 @@ pub fn dequeue<T, E, F>(f: F) -> Result<T, E>
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debug_assert!(!empty());
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unsafe {
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board::flush_cpu_dcache();
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cache::flush_cpu_dcache();
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let slice = slice::from_raw_parts_mut(read_volatile(RECV_MAILBOX) as *mut u8, QUEUE_CHUNK);
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f(slice).and_then(|x| {
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write_volatile(RECV_MAILBOX, next(read_volatile(RECV_MAILBOX)));
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