forked from M-Labs/artiq
LaneDistributor: style and signal consolidation [NFC]
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@ -28,7 +28,8 @@ class LaneDistributor(Module):
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# an underflow, at the time when the CRI write happens, and to a channel
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# an underflow, at the time when the CRI write happens, and to a channel
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# with zero latency compensation. This is synchronous to the system clock
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# with zero latency compensation. This is synchronous to the system clock
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# domain.
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# domain.
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self.minimum_coarse_timestamp = Signal(64-glbl_fine_ts_width)
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us_timestamp_width = 64 - glbl_fine_ts_width
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self.minimum_coarse_timestamp = Signal(us_timestamp_width)
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self.output = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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self.output = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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@ -50,10 +51,10 @@ class LaneDistributor(Module):
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current_lane = Signal(max=lane_count)
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current_lane = Signal(max=lane_count)
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# The last coarse timestamp received from the CRI, after compensation.
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# The last coarse timestamp received from the CRI, after compensation.
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# Used to determine when to switch lanes.
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# Used to determine when to switch lanes.
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last_coarse_timestamp = Signal(64-glbl_fine_ts_width)
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last_coarse_timestamp = Signal(us_timestamp_width)
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# The last coarse timestamp written to each lane. Used to detect
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# The last coarse timestamp written to each lane. Used to detect
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# sequence errors.
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# sequence errors.
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last_lane_coarse_timestamps = Array(Signal(64-glbl_fine_ts_width)
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last_lane_coarse_timestamps = Array(Signal(us_timestamp_width)
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for _ in range(lane_count))
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for _ in range(lane_count))
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# Sequence number counter. The sequence number is used to determine which
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# Sequence number counter. The sequence number is used to determine which
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# event wins during a replace.
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# event wins during a replace.
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@ -72,7 +73,6 @@ class LaneDistributor(Module):
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self.comb += lio.payload.data.eq(self.cri.o_data)
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self.comb += lio.payload.data.eq(self.cri.o_data)
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# when timestamp and channel arrive in cycle #1, prepare computations
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# when timestamp and channel arrive in cycle #1, prepare computations
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us_timestamp_width = 64 - glbl_fine_ts_width
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coarse_timestamp = Signal(us_timestamp_width)
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coarse_timestamp = Signal(us_timestamp_width)
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self.comb += coarse_timestamp.eq(self.cri.timestamp[glbl_fine_ts_width:])
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self.comb += coarse_timestamp.eq(self.cri.timestamp[glbl_fine_ts_width:])
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min_minus_timestamp = Signal((us_timestamp_width + 1, True))
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min_minus_timestamp = Signal((us_timestamp_width + 1, True))
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@ -96,6 +96,7 @@ class LaneDistributor(Module):
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for channel in quash_channels:
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for channel in quash_channels:
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self.sync += If(self.cri.chan_sel[:16] == channel, quash.eq(1))
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self.sync += If(self.cri.chan_sel[:16] == channel, quash.eq(1))
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assert all(abs(c) < 1 << 14 - 1 for c in compensation)
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latency_compensation = Memory(14, len(compensation), init=compensation)
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latency_compensation = Memory(14, len(compensation), init=compensation)
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latency_compensation_port = latency_compensation.get_port()
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latency_compensation_port = latency_compensation.get_port()
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self.specials += latency_compensation, latency_compensation_port
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self.specials += latency_compensation, latency_compensation_port
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@ -105,6 +106,7 @@ class LaneDistributor(Module):
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compensation = Signal((14, True))
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compensation = Signal((14, True))
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self.comb += compensation.eq(latency_compensation_port.dat_r)
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self.comb += compensation.eq(latency_compensation_port.dat_r)
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timestamp_above_min = Signal()
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timestamp_above_min = Signal()
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timestamp_above_last = Signal()
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timestamp_above_laneA_min = Signal()
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timestamp_above_laneA_min = Signal()
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timestamp_above_laneB_min = Signal()
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timestamp_above_laneB_min = Signal()
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timestamp_above_lane_min = Signal()
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timestamp_above_lane_min = Signal()
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@ -119,8 +121,9 @@ class LaneDistributor(Module):
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timestamp_above_min.eq(min_minus_timestamp - compensation < 0),
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timestamp_above_min.eq(min_minus_timestamp - compensation < 0),
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timestamp_above_laneA_min.eq(laneAmin_minus_timestamp - compensation < 0),
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timestamp_above_laneA_min.eq(laneAmin_minus_timestamp - compensation < 0),
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timestamp_above_laneB_min.eq(laneBmin_minus_timestamp - compensation < 0),
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timestamp_above_laneB_min.eq(laneBmin_minus_timestamp - compensation < 0),
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If(force_laneB | (last_minus_timestamp - compensation >= 0),
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timestamp_above_last.eq(last_minus_timestamp - compensation < 0),
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use_lanen.eq(current_lane + 1),
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If(force_laneB | ~timestamp_above_last,
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use_lanen.eq(current_lane_plus_one),
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use_laneB.eq(1)
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use_laneB.eq(1)
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).Else(
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).Else(
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use_lanen.eq(current_lane),
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use_lanen.eq(current_lane),
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@ -128,10 +131,16 @@ class LaneDistributor(Module):
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),
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),
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timestamp_above_lane_min.eq(Mux(use_laneB, timestamp_above_laneB_min, timestamp_above_laneA_min)),
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timestamp_above_lane_min.eq(Mux(use_laneB, timestamp_above_laneB_min, timestamp_above_laneA_min)),
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If(~quash,
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If(~quash & (self.cri.cmd == cri.commands["write"]),
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do_write.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & timestamp_above_lane_min),
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If(timestamp_above_min,
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do_underflow.eq((self.cri.cmd == cri.commands["write"]) & ~timestamp_above_min),
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If(timestamp_above_lane_min,
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do_sequence_error.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & ~timestamp_above_lane_min),
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do_write.eq(1)
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).Else(
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do_sequence_error.eq(1)
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)
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).Else(
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do_underflow.eq(1)
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)
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),
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),
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Array(lio.we for lio in self.output)[use_lanen].eq(do_write)
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Array(lio.we for lio in self.output)[use_lanen].eq(do_write)
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]
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]
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@ -139,7 +148,7 @@ class LaneDistributor(Module):
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self.comb += compensated_timestamp.eq(self.cri.timestamp + (compensation << glbl_fine_ts_width))
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self.comb += compensated_timestamp.eq(self.cri.timestamp + (compensation << glbl_fine_ts_width))
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self.sync += [
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self.sync += [
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If(do_write,
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If(do_write,
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If(use_laneB, current_lane.eq(current_lane + 1)),
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current_lane.eq(use_lanen),
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last_coarse_timestamp.eq(compensated_timestamp[glbl_fine_ts_width:]),
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last_coarse_timestamp.eq(compensated_timestamp[glbl_fine_ts_width:]),
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last_lane_coarse_timestamps[use_lanen].eq(compensated_timestamp[glbl_fine_ts_width:]),
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last_lane_coarse_timestamps[use_lanen].eq(compensated_timestamp[glbl_fine_ts_width:]),
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seqn.eq(seqn + 1),
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seqn.eq(seqn + 1),
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@ -77,12 +77,15 @@ def simulate(input_events, compensation=None, wait=True):
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class TestLaneDistributor(unittest.TestCase):
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class TestLaneDistributor(unittest.TestCase):
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def test_regular(self):
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def test_regular(self):
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# N sequential events, all on lane 0
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N = 16
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N = 16
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output, access_results = simulate([(42+n, (n+1)*8) for n in range(N)], wait=False)
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output, access_results = simulate([(42+n, (n+1)*8) for n in range(N)], wait=False)
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self.assertEqual(output, [(0, n, 42+n, (n+1)*8) for n in range(N)])
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self.assertEqual(output, [(0, n, 42+n, (n+1)*8) for n in range(N)])
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self.assertEqual(access_results, [("ok", 0)]*N)
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self.assertEqual(access_results, [("ok", 0)]*N)
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def test_wait_time(self):
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def test_wait_time(self):
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# LANE_COUNT simultaneous events should be distributed and written to
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# the lanes when the latter are writable
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output, access_results = simulate([(42+n, 8) for n in range(LANE_COUNT)])
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output, access_results = simulate([(42+n, 8) for n in range(LANE_COUNT)])
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self.assertEqual(output, [(n, n, 42+n, 8) for n in range(LANE_COUNT)])
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self.assertEqual(output, [(n, n, 42+n, 8) for n in range(LANE_COUNT)])
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expected_access_results = [("ok", 0)]*LANE_COUNT
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expected_access_results = [("ok", 0)]*LANE_COUNT
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@ -91,33 +94,40 @@ class TestLaneDistributor(unittest.TestCase):
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self.assertEqual(access_results, expected_access_results)
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self.assertEqual(access_results, expected_access_results)
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def test_lane_switch(self):
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def test_lane_switch(self):
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# N events separated by one fine timestamp distributed onto lanes
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# LANE_COUNT == 1 << fine_ts_width
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N = 32
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N = 32
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output, access_results = simulate([(42+n, n+8) for n in range(N)], wait=False)
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output, access_results = simulate([(42+n, n+8) for n in range(N)], wait=False)
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self.assertEqual(output, [((n-n//8) % LANE_COUNT, n, 42+n, n+8) for n in range(N)])
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self.assertEqual(output, [((n-n//8) % LANE_COUNT, n, 42+n, n+8) for n in range(N)])
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self.assertEqual([ar[0] for ar in access_results], ["ok"]*N)
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self.assertEqual([ar[0] for ar in access_results], ["ok"]*N)
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def test_sequence_error(self):
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def test_sequence_error(self):
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# LANE_COUNT + 1 simultaneous events, the last one being discarded due
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# to sequence error, followed by a valid event
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input_events = [(42+n, 8) for n in range(LANE_COUNT+1)]
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input_events = [(42+n, 8) for n in range(LANE_COUNT+1)]
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input_events.append((42+LANE_COUNT+1, 16))
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input_events.append((42+LANE_COUNT+1, 16))
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output, access_results = simulate(input_events)
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output, access_results = simulate(input_events)
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self.assertEqual(len(output), len(input_events)-1) # event with sequence error must get discarded
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self.assertEqual(len(output), len(input_events)-1) # event with sequence error must get discarded
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self.assertEqual(output[-1], (0, LANE_COUNT, 42+LANE_COUNT+1, 16))
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self.assertEqual([ar[0] for ar in access_results[:LANE_COUNT]], ["ok"]*LANE_COUNT)
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self.assertEqual([ar[0] for ar in access_results[:LANE_COUNT]], ["ok"]*LANE_COUNT)
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self.assertEqual(access_results[LANE_COUNT][0], "sequence_error")
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self.assertEqual(access_results[LANE_COUNT][0], "sequence_error")
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self.assertEqual(access_results[LANE_COUNT + 1][0], "ok")
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def test_underflow(self):
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def test_underflow(self):
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# N sequential events except the penultimate which underflows
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N = 16
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N = 16
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input_events = [(42+n, (n+1)*8) for n in range(N-2)]
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input_events = [(42+n, (n+1)*8) for n in range(N)]
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input_events.append((0, 0)) # timestamp < 8 underflows
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input_events[-2] = (0, 0) # timestamp < 8 underflows
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input_events.append((42+N-2, N*8))
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output, access_results = simulate(input_events)
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output, access_results = simulate(input_events)
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self.assertEqual(len(output), len(input_events)-1) # event with underflow must get discarded
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self.assertEqual(len(output), len(input_events)-1) # event with underflow must get discarded
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self.assertEqual([ar[0] for ar in access_results[:N-2]], ["ok"]*(N-2))
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self.assertEqual([ar[0] for ar in access_results[:N-2]], ["ok"]*(N-2))
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self.assertEqual(access_results[N-2][0], "underflow")
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self.assertEqual(access_results[N-2][0], "underflow")
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self.assertEqual(output[N-2], (0, N-2, 42+N-2, N*8))
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self.assertEqual(output[N-2], (0, N-2, 42+N-1, N*8))
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self.assertEqual(access_results[N-1][0], "ok")
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self.assertEqual(access_results[N-1][0], "ok")
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def test_spread(self):
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def test_spread(self):
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# get to lane 6
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# 6 simultaneous events to reach lane 6 and 7 which are not writable
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# for 1 and 4 cycles respectively causing a forced lane switch
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input_events = [(42+n, 8) for n in range(7)]
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input_events = [(42+n, 8) for n in range(7)]
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input_events.append((100, 16))
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input_events.append((100, 16))
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input_events.append((100, 32))
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input_events.append((100, 32))
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