Merge branch 'ppp2'

The command to establish the PP link to the core device is:

  pppd /dev/ttyUSB1 115200 noauth nodetach local nocrtscts novj \
    10.0.0.1:10.0.0.2

The "novj" can be dropped once lwip fixes VJ IP header compression.
Current LWIP (4beacc4) may have fixed that but breaks something else (crashes).

* ppp2:
  ppp: update documentation
  ppp: remove unneeded objects
  ppp: wait for connection
  PPP support (TCP broken)
  pipistrello: add rtio.Analyzer()

artiq/coredevice/comm_serial.py

@@ -1,42 +0,0 @@
-import logging
-import serial
-import struct
-
-from artiq.coredevice.comm_generic import CommGeneric
-
-
-logger = logging.getLogger(__name__)
-
-
-class Comm(CommGeneric):
-    def __init__(self, dmgr, serial_dev, baud_rate=115200):
-        super().__init__()
-        self.serial_dev = serial_dev
-        self.baud_rate = baud_rate
-
-    def open(self):
-        if hasattr(self, "port"):
-            return
-        self.port = serial.serial_for_url(self.serial_dev,
-                                          baudrate=self.baud_rate)
-        self.reset_session()
-
-    def close(self):
-        if not hasattr(self, "port"):
-            return
-        self.port.close()
-        del self.port
-
-    def read(self, length):
-        result = bytes()
-        while len(result) < length:
-            result += self.port.read(length - len(result))
-        return result
-
-    def write(self, data):
-        remaining = len(data)
-        pos = 0
-        while remaining:
-            written = self.port.write(data[pos:])
-            remaining -= written
-            pos += written

artiq/gateware/targets/pipistrello.py

@@ -106,7 +106,8 @@ class NIST_QC1(BaseSoC, AMPSoC):
         "rtio": None,  # mapped on Wishbone instead
         "rtio_crg": 10,
         "kernel_cpu": 11,
-        "rtio_moninj": 12
+        "rtio_moninj": 12,
+        "rtio_analyzer": 13
     }
     csr_map.update(BaseSoC.csr_map)
     mem_map = {
@@ -208,6 +209,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
                             rtio_csrs)
 
+        self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
+            self.get_native_sdram_if())
+
 
 def main():
     parser = argparse.ArgumentParser(

artiq/runtime/liblwip/Makefile

@@ -19,7 +19,6 @@ COREFILES=core/mem.c \
 	core/tcp_in.c \
 	core/tcp_out.c \
 	core/udp.c \
-	core/dhcp.c \
 	core/inet_chksum.c \
 	core/timers.c \
 	core/init.c
@@ -32,8 +31,18 @@ CORE4FILES=core/ipv4/icmp.c \
 # NETIFFILES: Files implementing various generic network interface functions.
 NETIFFILES=netif/etharp.c
 
+PPPFILES=netif/ppp/auth.c \
+	netif/ppp/fsm.c \
+	netif/ppp/ipcp.c \
+	netif/ppp/lcp.c \
+	netif/ppp/magic.c \
+	netif/ppp/ppp.c \
+	netif/ppp/pppos.c \
+	netif/ppp/utils.c \
+	netif/ppp/vj.c
+
 # LWIPFILES: All the above.
-LWIPFILES=$(COREFILES) $(CORE4FILES) $(NETIFFILES)
+LWIPFILES=$(COREFILES) $(CORE4FILES) $(NETIFFILES) $(PPPFILES)
 
 LWIPOBJS:=$(LWIPFILES:.c=.o) liteethif.o
 
@@ -46,6 +55,7 @@ prepare:
 	ln -s $(LIBLWIP_DIRECTORY)/arch arch
 	mkdir -p core/ipv4
 	mkdir -p netif
+	mkdir -p netif/ppp
 
 core/%.o: $(LWIPDIR)/core/%.c
 	$(compile)
@@ -56,6 +66,9 @@ core/ipv4/%.o: $(LWIPDIR)/core/ipv4/%.c
 netif/%.o: $(LWIPDIR)/netif/%.c
 	$(compile)
 
+netif/ppp/%.o: $(LWIPDIR)/netif/ppp/%.c
+	$(compile)
+
 %.o: $(LIBLWIP_DIRECTORY)/%.c
 	$(compile)
 

artiq/runtime/liblwip/lwipopts.h

@@ -181,4 +181,10 @@ a lot of data that needs to be copied, this should be set high. */
 #define SYS_STATS
 #endif /* STATS */
 
+/* ---------- PPP ---------- */
+
+#define PPP_SUPPORT 1
+#define PPPOS_SUPPORT 1
+#define PPP_IPV4_SUPPORT 1
+
 #endif /* __LWIPOPTS_H__ */

artiq/runtime/main.c

@@ -8,7 +8,6 @@
 #include <generated/csr.h>
 #include <hw/flags.h>
 
-#ifdef CSR_ETHMAC_BASE
 #include <lwip/init.h>
 #include <lwip/memp.h>
 #include <lwip/ip4_addr.h>
@@ -17,8 +16,13 @@
 #include <lwip/sys.h>
 #include <lwip/tcp.h>
 #include <lwip/timers.h>
+#ifdef CSR_ETHMAC_BASE
 #include <netif/etharp.h>
 #include <liteethif.h>
+#else
+#include <netif/ppp/ppp.h>
+#include <netif/ppp/pppos.h>
+#include <lwip/sio.h>
 #endif
 
 #include "bridge_ctl.h"
@@ -32,24 +36,40 @@
 #include "analyzer.h"
 #include "moninj.h"
 
-#ifdef CSR_ETHMAC_BASE
-
 u32_t sys_now(void)
 {
     return clock_get_ms();
 }
 
+u32_t sys_jiffies(void)
+{
+    return clock_get_ms();
+}
+
 static struct netif netif;
 
+#ifndef CSR_ETHMAC_BASE
+static ppp_pcb *ppp;
+#endif
+
 static void lwip_service(void)
 {
     sys_check_timeouts();
+#ifdef CSR_ETHMAC_BASE
     if(ethmac_sram_writer_ev_pending_read() & ETHMAC_EV_SRAM_WRITER) {
         liteeth_input(&netif);
         ethmac_sram_writer_ev_pending_write(ETHMAC_EV_SRAM_WRITER);
     }
+#else
+    if(uart_read_nonblock()) {
+        u8_t c;
+        c = uart_read();
+        pppos_input(ppp, &c, 1);
+    }
+#endif
 }
 
+#ifdef CSR_ETHMAC_BASE
 unsigned char macadr[6];
 
 static int hex2nib(int c)
@@ -128,6 +148,47 @@ static void network_init(void)
     netif_set_up(&netif);
     netif_set_link_up(&netif);
 }
+#else /* CSR_ETHMAC_BASE */
+
+static int ppp_connected;
+
+static void ppp_status_cb(ppp_pcb *pcb, int err_code, void *ctx)
+{
+  if (err_code == PPPERR_NONE) {
+    ppp_connected = 1;
+    return;
+  } else if (err_code == PPPERR_USER) {
+    return;
+  } else {
+    ppp_connect(pcb, 10);
+  }
+}
+
+u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len)
+{
+    int i;
+
+    for(i=0;i<len;i++)
+        uart_write(data[i]);
+    return len;
+}
+
+static void network_init(void)
+{
+    lwip_init();
+
+    ppp_connected = 0;
+    ppp = pppos_create(&netif, NULL, ppp_status_cb, NULL);
+    ppp_set_auth(ppp, PPPAUTHTYPE_NONE, "", "");
+    ppp_set_default(ppp);
+    ppp_connect(ppp, 0);
+
+    while (!ppp_connected)
+        lwip_service();
+}
+
+#endif /* CSR_ETHMAC_BASE */
+
 
 static struct net_server_instance session_inst = {
     .port = 1381,
@@ -153,7 +214,7 @@ static struct net_server_instance analyzer_inst = {
 
 static void regular_main(void)
 {
-    puts("Accepting sessions on Ethernet.");
+    puts("Accepting sessions on Network.");
     network_init();
     net_server_init(&session_inst);
 #ifdef CSR_RTIO_ANALYZER_BASE
@@ -170,69 +231,6 @@ static void regular_main(void)
     }
 }
 
-#else /* CSR_ETHMAC_BASE */
-
-static void reset_serial_session(int signal)
-{
-    int i;
-
-    session_end();
-    if(signal) {
-        /* Signal end-of-session inband with zero length packet. */
-        for(i=0;i<4;i++)
-            uart_write(0x5a);
-        for(i=0;i<4;i++)
-            uart_write(0x00);
-    }
-    session_start();
-}
-
-static void serial_service(void)
-{
-    char *txdata;
-    int txlen;
-    static char rxdata;
-    static int rxpending;
-    int r, i;
-
-    if(!rxpending && uart_read_nonblock()) {
-        rxdata = uart_read();
-        rxpending = 1;
-    }
-    if(rxpending) {
-        r = session_input(&rxdata, 1);
-        if(r > 0)
-            rxpending = 0;
-        if(r < 0)
-            /* do not signal if reset was requested by host */
-            reset_serial_session(r != -2);
-    }
-
-    session_poll((void **)&txdata, &txlen);
-    if(txlen > 0) {
-        for(i = 0; i < txlen; i++)
-            uart_write(txdata[i]);
-        session_ack_consumed(txlen);
-        session_ack_sent(txlen);
-    } else if(txlen < 0) {
-        reset_serial_session(1);
-    }
-}
-
-static void regular_main(void)
-{
-    puts("Accepting sessions on serial link.");
-
-    /* Open the session for the serial control. */
-    session_start();
-    while(1) {
-        kloader_service_essential_kmsg();
-        serial_service();
-    }
-}
-
-#endif
-
 static void blink_led(void)
 {
     int i;

artiq/runtime/moninj.c

@@ -1,8 +1,5 @@
 #include <generated/csr.h>
 
-#ifdef CSR_ETHMAC_BASE
-
-#include <netif/etharp.h>
 #include <lwip/init.h>
 #include <lwip/memp.h>
 #include <lwip/ip4_addr.h>
@@ -152,5 +149,3 @@ void moninj_init(void)
     udp_bind(listen_pcb, IP_ADDR_ANY, 3250);
     udp_recv(listen_pcb, moninj_recv, NULL);
 }
-
-#endif /* CSR_ETHMAC_BASE */

artiq/runtime/net_server.c

@@ -1,7 +1,5 @@
 #include <generated/csr.h>
 
-#ifdef CSR_ETHMAC_BASE
-
 #include <lwip/init.h>
 #include <lwip/memp.h>
 #include <lwip/ip4_addr.h>
@@ -10,8 +8,6 @@
 #include <lwip/sys.h>
 #include <lwip/tcp.h>
 #include <lwip/timers.h>
-#include <netif/etharp.h>
-#include <liteethif.h>
 
 #include "net_server.h"
 
@@ -227,5 +223,3 @@ void net_server_service(void)
         pcb = pcb->next;
     }
 }
-
-#endif /* CSR_ETHMAC_BASE */

doc/manual/core_device.rst

@@ -69,7 +69,9 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
 Pipistrello
 -----------
 
-The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alternative. The current USB over serial protocol also suffers from limitations (no monitoring/injection, no idle experiment, no kernel interruptions, lack of robustness).
+The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alternative. Since the device does not have a native network interface, a PPP session is run over the serial port (which is then run over USB). To establish the PPP session with the core device, giving it the IP address 10.0.0.2, as root execute::
+
+    pppd /dev/ttyUSB1 115200 noauth nodetach local nocrtscts novj 10.0.0.1:10.0.0.2
 
 When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows: