forked from M-Labs/artiq
targets/pipistrello: work around Xst placer idiocy
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@ -153,6 +153,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
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platform = self.platform
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platform = self.platform
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platform.toolchain.map_opt += " -t 40"
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platform.toolchain.bitgen_opt += " -g compress"
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platform.toolchain.bitgen_opt += " -g compress"
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platform.toolchain.ise_commands += """
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platform.toolchain.ise_commands += """
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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