From 2c0b6ff4cc72a515649e67f28818e012d06cfab8 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 11 Sep 2014 23:11:22 +0800 Subject: [PATCH] soc/target: connect FUD to RTIO --- soc/targets/artiq.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py index 811ab1784..9f85a7137 100644 --- a/soc/targets/artiq.py +++ b/soc/targets/artiq.py @@ -43,12 +43,17 @@ class ARTIQMiniSoC(BaseSoC): self.comb += platform.request("ttl_tx_en").eq(1) rtio_pads = [platform.request("ttl", i) for i in range(4)] + fud = Signal() + rtio_pads.append(fud) self.submodules.rtiophy = rtio.phy.SimplePHY( rtio_pads, - {rtio_pads[1], rtio_pads[2], rtio_pads[3]}) + output_only_pads={rtio_pads[1], rtio_pads[2], rtio_pads[3]}, + mini_pads={fud}) self.submodules.rtio = rtio.RTIO(self.rtiophy) - self.submodules.dds = ad9858.AD9858(platform.request("dds")) + dds_pads = platform.request("dds") + self.submodules.dds = ad9858.AD9858(dds_pads) self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus) + self.comb += dds_pads.fud_n.eq(~fud) default_subtarget = ARTIQMiniSoC