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pipistrello: shrink a few more fifos

This commit is contained in:
Robert Jördens 2016-09-21 02:29:05 +02:00
parent 9a24a81f14
commit 2bb90a4449
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/targets/pipistrello.py
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@ -176,7 +176,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
ofifo_depth=4))
# the last TTL is used for ClockGen
@ -223,7 +223,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
phy = dds.AD9858(dds_pins, 8)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=256,
ofifo_depth=128,
ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)