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phaser: stpl

This commit is contained in:
Robert Jördens 2016-10-11 19:23:13 +02:00
parent e4d1f6cf1f
commit 2b1cca2e7e
2 changed files with 54 additions and 0 deletions
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45
artiq/examples/phaser/repository/test_ad9154_stpl.py Normal file
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@ -0,0 +1,45 @@
import time
from artiq.coredevice.ad9154_reg import *
from artiq.experiment import *
class Test(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("ad9154")
def run(self):
self.stpl()
def stpl(self):
# short transport layer test
for i, data in enumerate([0x0123, 0x4567, 0x89ab, 0xcdef]):
# select dac
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(0) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# set expected value
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
# enable stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# reset stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(1) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
# release reset stpl
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(1) |
AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0))
print("c{:d}: {:d}".format(i, self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)))

9
artiq/gateware/targets/kc705.py
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@ -543,6 +543,15 @@ class Phaser(_NIST_Ions):
"converter{}".format(i)) "converter{}".format(i))
# while at 5 GBps, take every second sample... FIXME # while at 5 GBps, take every second sample... FIXME
self.comb += conv.eq(Cat(ch.o[::2])) self.comb += conv.eq(Cat(ch.o[::2]))
# short transport layer test pattern
self.comb += [
self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123),
self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567),
self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab),
self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef)
]
self.comb += jesd_sync.eq(self.ad9154.jesd_sync) self.comb += jesd_sync.eq(self.ad9154.jesd_sync)