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sayma: remove SYSREF DDMTD core (#1420)

This commit is contained in:
Sebastien Bourdeauducq 2020-01-19 23:31:54 +08:00
parent 622dad9bd9
commit 2ad7d2967a
2 changed files with 1 additions and 7 deletions
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2
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -154,7 +154,7 @@ pub mod hmc7043 {
(true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK
(true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF
(true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0
(true, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
(false, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
(false, 0, 0x10, false), // 6: unused
(true, SYSREF_DIV, 0x10, true), // 7: RTM_FPGA_SYSREF0
(true, FPGA_CLK_DIV, 0x08, false), // 8: GTP_CLK0_IN

6
artiq/gateware/targets/sayma_amc.py
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@ -288,12 +288,6 @@ class Satellite(SatelliteBase):
self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
# DDMTD
# https://github.com/sinara-hw/Sayma_RTM/issues/68
sysref_pads = platform.request("amc_fpga_sysref", 1)
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
self.csr_devices.append("sysref_ddmtd")
class SimpleSatellite(SatelliteBase):
def __init__(self, **kwargs):